ChanServ changed the topic of #amaranth-lang to: Amaranth hardware description language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<_whitenotifier-e> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JDOpD
<_whitenotifier-e> [YoWASP/yosys] whitequark 1f8dd55 - Update dependencies.
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<Qyriad> (Bridge test from IRC)
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<d1b2> <Qyriad> (Testing in production go brrr)
<Qyriad> (Thank gods — test from the other end?)
<d1b2> <sys64738> seems to work
<d1b2> <Qyriad> Yep, migration complete I think
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<d1b2> <esden> Thank you @Qyriad 😄
<d1b2> <Qyriad> No problem~
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<modwizcode> <Qyriad> "(Bridge test from IRC)" <- what were you testing?
<d1b2> <david.lenfesty> the 1bitsquared discord bridge
<Qyriad> The IRC-Discord bridge for the 1BitSquared Discord ser— yes
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<cr1901> discord-irc is fun. I ran it for a bit on an ARM SBC to serve as a bridge for a few channels
<cr1901> turns out a VPS is better for this
<cr1901> go figure
<d1b2> <sajattack> why was nmigen renamed? and respectfully, why is the name that was chosen close to the twitch bathwater girl's name?
<cr1901> it's the name of a song from a band that I'm _guessing_ wq likes?
<cr1901> No relation to bathwater girl
<tpw_rules> it's also a plant. and the girl i vaguely remember was not similar at all...?
<cr1901> I think others can do a better job explaining why the name was changed tho
<d1b2> <sajattack> just seems like a bad name association, like when my company almost named something ProStat before they realized it was too close to prostate
<d1b2> <sajattack> but I guess it's too late now xD
<d1b2> <dragonmux> has less than no clue as to the twitch reference
<d1b2> <dragonmux> as for the reasoning, as far as we're aware it's two fold - the first part is to distance the project from m-labs after all the harm that's been caused there, and the second is to solve the issues surrounding the constant mixups the project was seeing with the dead predecessor repo
<d1b2> <emeb> It's a good name.
<d1b2> <dragonmux> personally we love the name esp as it reminds us of the flower and some music we enjoy from Nightwish
<d1b2> <sajattack> I guess this is my zoomer showing
<d1b2> <sajattack> so long as y'all know what you're a homonym with and are ok with it, doesn't really matter to me
<tpw_rules> my favorite feature is i can pronounce it
<eigenform> wikipedia describes the flowers as "catkin-like" and i refuse to believe that is a coincidence
<emeb_mac> +1
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JD3Dj
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] miek da9d38e - Fix README links.
<_whitenotifier-e> [amaranth-yosys] whitequark closed pull request #3: Fix README links. - https://git.io/JDOM5
<_whitenotifier-e> [amaranth-yosys] whitequark commented on pull request #3: Fix README links. - https://git.io/JD3ye
<whitequark> I didn't know about the Twitch streamer, but honestly, I don't consider it an issue either way
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<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±2] https://git.io/JD3HM
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 0fb2b4c - docs: fix download link in start.rst.
<_whitenotifier-e> [amaranth] whitequark closed issue #647: Download link is wrong on https://nmigen.info/nmigen/latest/start.html - https://git.io/JD3HD
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+1/-0/±15] https://git.io/JD3HF
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 9190ea9 - Deploying to gh-pages from @ 0fb2b4cd39644d296a0372326ff03f28edcd6096 🚀
whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±2] https://git.io/JD3jM
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark de7c9ac - _utils: don't crash trying to flatten() strings.
<_whitenotifier-e> [amaranth] whitequark closed issue #614: bad error message when giving Cat strings - https://git.io/JD3jD
<_whitenotifier-e> [amaranth] whitequark commented on issue #614: bad error message when giving Cat strings - https://git.io/JD3j9
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JD3jF
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 2f738cd - Deploying to gh-pages from @ de7c9acb194ba591bfb13ada75f4a7e4a300b641 🚀
<_whitenotifier-e> [amaranth] whitequark commented on issue #570: Download link on Getting started doc page is broken - https://git.io/JDsel
<_whitenotifier-e> [amaranth] whitequark closed issue #570: Download link on Getting started doc page is broken - https://git.io/JDse8
<_whitenotifier-e> [amaranth] whitequark commented on issue #587: Enable githubs discussion tab - https://git.io/JDsvv
<_whitenotifier-e> [amaranth] whitequark closed issue #587: Enable githubs discussion tab - https://git.io/JDsvf
<_whitenotifier-e> [amaranth] modwizcode commented on issue #608: [RFC] get rid of that `+=` and `.eq()` - https://git.io/JDsvZ
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±2] https://git.io/JDsIE
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 44b8bd2 - hdl.ast: warn on bare integer value used in Cat()/Repl().
<_whitenotifier-e> [amaranth] whitequark closed issue #639: Consider issuing a warning when a bare integer is used in Cat() or Repl() - https://git.io/JDsIu
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDsIV
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 139d4f4 - Deploying to gh-pages from @ 44b8bd29af097c61bb84a559041dffb3b41232bf 🚀
<whitequark> er, wrong window
<whitequark> though I think some of you might find the hook useful
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<kaucasus> Congrats on the name change! I have a small question about the built-in memory module. When updating it via the write port, I'd assume that something like `m.d.comb += write_port.data[0:16].eq(
<kaucasus>                         self.i_write_data)` would only update the 16 LSBs of the memory cell. (with the memory a width of 32 bits and i_write_data a signal of 16 bits). Instead the MSBs are set to zero. E.g. if the original value is DEADBEEF, i_write_data is CAFE, then I'd expect the memory to have DEADCAFE, instead it is
<kaucasus> 0000CAFE. Is there a way to get around that or is it just working as intended?
<whitequark> you need to request a write port with a granularity lower than the memory width, and use enable signals to update only a part of the memory
<whitequark> so, use `write_port = mem.write_port(granularity=16)`; then `write_port.en.eq(0b01)` to update LSBs only
<kaucasus> Ahhhhh that's way more elegant than what I'd had in mind! Thanks!
<d1b2> <dub_dub_11> That makes two metal links 😄 with also the band Amaranthe with an e
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] whitequark pushed 2 commits to develop [+0/-0/±3] https://git.io/JDslk
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] whitequark ab677d1 - Require wasmtime>=0.30,<0.32.
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] whitequark 489dffd - Update yosys.
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<_whitenotifier-e> [amaranth-lang/amaranth-yosys] whitequark pushed 3 commits to release [+0/-0/±4] https://git.io/JDsBz
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] miek da9d38e - Fix README links.
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] whitequark ab677d1 - Require wasmtime>=0.30,<0.32.
<_whitenotifier-e> [amaranth-lang/amaranth-yosys] whitequark 489dffd - Update yosys.
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<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±1] https://git.io/JDsu0
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 25573c5 - back.rtlil: extend unsigned operand of binop if another is signed.
<_whitenotifier-e> [amaranth] whitequark closed issue #580: Signed comparison -- difference between sim and Verilog generation - https://git.io/JDsuE
<_whitenotifier-e> [amaranth] whitequark commented on issue #580: Signed comparison -- difference between sim and Verilog generation - https://git.io/JDsuu
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDsua
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 9558811 - Deploying to gh-pages from @ 25573c5eff336bb0fbd034a74f8a25820017ed4c 🚀
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±9] https://git.io/JDszT
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark b452e0e - hdl.ast: support division and modulo with negative divisor.
<_whitenotifier-e> [amaranth] whitequark closed issue #621: nMigen thinks -5 / 2 = 3 - https://git.io/JDszk
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±18] https://git.io/JDsz3
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark f2f405f - Deploying to gh-pages from @ b452e0e87172c673a9b8beae6497c96a281eb983 🚀
<_whitenotifier-e> [amaranth] whitequark commented on issue #621: nMigen thinks -5 / 2 = 3 - https://git.io/JDszZ
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<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±2] https://git.io/JDsoB
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 66295fa - sim.pysim: refuse to write VCD files with whitespace in signal names.
<_whitenotifier-e> [amaranth] whitequark closed pull request #595: raise error on space in fsm name - https://git.io/JDsoR
<_whitenotifier-e> [amaranth] whitequark commented on pull request #595: raise error on space in fsm name - https://git.io/JDso2
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDsor
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark b941d43 - Deploying to gh-pages from @ 66295fa388be1d92f038f390e5aea937b5e5c01b 🚀
<_whitenotifier-e> [amaranth] whitequark commented on issue #558: write_cfgmem is writing to arty board when not specified to in the code - https://git.io/JDsoF
<_whitenotifier-e> [amaranth] whitequark closed issue #558: write_cfgmem is writing to arty board when not specified to in the code - https://git.io/JDsob
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<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±2] https://git.io/JDsPY
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark fd7d01e - back.rtlil,cli: allow suppressing generation of `src` attributes.
<_whitenotifier-e> [amaranth] whitequark closed issue #572: Add option to suppress code generation comments - https://git.io/JDsP3
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDsPW
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 9c89bc7 - Deploying to gh-pages from @ fd7d01ef1076ab0a2e2fa9d150eee258d6b10561 🚀
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<_whitenotifier-e> [amaranth] modwizcode opened pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsDz
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<_whitenotifier-e> [amaranth] whitequark commented on issue #635: empty signal slice generates verilog which can not be parsed by Quartus - https://git.io/JDsDr
<_whitenotifier-e> [amaranth] whitequark closed issue #635: empty signal slice generates verilog which can not be parsed by Quartus - https://git.io/JDsDo
<_whitenotifier-e> [amaranth] codecov-commenter commented on pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsDd
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsDd
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsDd
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsDd
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsDd
<_whitenotifier-e> [amaranth] whitequark closed pull request #606: Feature/vivado synth opts - https://git.io/JDsyL
<_whitenotifier-e> [amaranth] whitequark closed pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsDz
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±1] https://git.io/JDsyt
<_whitenotifier-e> [amaranth-lang/amaranth] modwizcode b1eba5f - vendor.xilinx: support setting options on synth_design
<_whitenotifier-e> [amaranth] whitequark commented on pull request #649: vendor.xilinx: support setting options on synth_design - https://git.io/JDsyq
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDsyn
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 0b6b9cc - Deploying to gh-pages from @ b1eba5fd82a84dd67a10f0eacb9921991d46c38d 🚀
<_whitenotifier-e> [amaranth] whitequark closed issue #625: Clock signal jumps two states with one edge - https://git.io/JDsyP
<_whitenotifier-e> [amaranth] whitequark commented on issue #437: Utilise `write_verilog -sv` for targets that support it - https://git.io/JDsHr
<_whitenotifier-e> [amaranth] whitequark commented on issue #592: Fragment.get should detect cycles in elaboration - https://git.io/JDs7W
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 2 commits to main [+0/-0/±8] https://git.io/JDs72
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 90777a6 - build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*.
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 599615e - hdl.ir: reject elaboratables that elaborate to themselves.
<_whitenotifier-e> [amaranth] whitequark closed issue #592: Fragment.get should detect cycles in elaboration - https://git.io/JDs7a
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDs7i
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark f830a44 - Deploying to gh-pages from @ 599615ee3a34dfd956e70d57fe56e73ef1d750c9 🚀
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<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±3] https://git.io/JDsbw
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark ac13a5b - sim._pyrtl: reject very large values.
<_whitenotifier-e> [amaranth] whitequark closed issue #588: Left shift + simulator = infinite (?) loop - https://git.io/JDsbr
<_whitenotifier-e> [amaranth] hansfbaier commented on issue #635: empty signal slice generates verilog which can not be parsed by Quartus - https://git.io/JDsb9
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDsbQ
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark c911ad5 - Deploying to gh-pages from @ ac13a5b3c92d41b44366d1cc3609051e80dfde67 🚀
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<_whitenotifier-e> [amaranth] whitequark commented on issue #566: Python simulator hangs or throws when trying to drive reset from testbench - https://git.io/JDsxQ
<rodrigomelo9> Hi. I want to try Amaranth as a top-level integration tool, to join System/Verilog already developed IPs (for an ASIC project). Are there examples/docs related to that? Of course, I am looking for advantages over a traditional Verilog top-level.
<modwizcode> I'm curious what sort of examples you'd be looking for? Either way you're just instantiating other modules from a top level design right?
<rodrigomelo9> Yes, but probably there exist some "magic" to easily interconnect buses, create registers, integrate with JSON/YAML, etc, that I don't know:P  (and I am not currently an Amaranth user)
<_whitenotifier-e> [amaranth] whitequark commented on issue #566: Python simulator hangs or throws when trying to drive reset from testbench - https://git.io/JDshA
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±2] https://git.io/JDsjJ
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 7e2b728 - sim.core: warn when driving a clock domain not in the simulation.
<_whitenotifier-e> [amaranth] whitequark closed issue #566: Python simulator hangs or throws when trying to drive reset from testbench - https://git.io/JDsjU
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDsjs
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 6b76749 - Deploying to gh-pages from @ 7e2b72826fbf795c555e971460123195dfd2898b 🚀
<modwizcode> oops
<modwizcode> <rodrigomelo9> "Yes, but probably there exist..." <- ah, we
<modwizcode> we're not aware of any but we would be curious if any are known
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±2] https://git.io/JDGfZ
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 7c16195 - build.dsl: check type of resource number.
<_whitenotifier-e> [amaranth] whitequark closed issue #599: Possibly-misleading error when forgetting the `number` argument to Resource `__init__`. - https://git.io/JDGfn
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDGfo
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark b556c2f - Deploying to gh-pages from @ 7c161957bfe35e27c98ac82777b3fc53564a28fc 🚀
<rodrigomelo9> Ok. I have a friend doing something related (not public). I will try to create an example and let you know.
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<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to cxxsim [+3/-0/±4] https://git.io/JDGq5
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark 1c0cf92 - [WIP] sim: add cxxsim engine.
<_whitenotifier-e> [amaranth] hansfbaier commented on issue #566: Python simulator hangs or throws when trying to drive reset from testbench - https://git.io/JDGGo
<_whitenotifier-e> [amaranth] jreyesr synchronize pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDGB1
<_whitenotifier-e> [amaranth] codecov-commenter commented on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDGBS
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDGBS
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDGBS
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDGBS
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDGBS
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDGBS
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<_whitenotifier-e> [amaranth] whitequark commented on issue #565: cxxsim: random garbage in memory traces - https://git.io/JDGgh
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<_whitenotifier-e> [amaranth] modwizcode opened pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDG1o
<_whitenotifier-e> [amaranth] codecov-commenter commented on pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDG1p
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDG1p
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDG1p
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDG1p
<_whitenotifier-e> [amaranth] codecov-commenter edited a comment on pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDG1p
<_whitenotifier-e> [amaranth] whitequark closed issue #605: Nesting Parts with a variable offset throws an AssertionError - https://git.io/JDGy7
<_whitenotifier-e> [amaranth] whitequark closed pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDG1o
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±1] https://git.io/JDGyd
<_whitenotifier-e> [amaranth-lang/amaranth] modwizcode 0b74d1c - back.rtlil: support slicing on Parts
<_whitenotifier-e> [amaranth] whitequark commented on pull request #650: back.rtlil: support slicing on Parts - https://git.io/JDGyF
<_whitenotifier-e> [amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JDGSU
<_whitenotifier-e> [amaranth-lang/amaranth] whitequark e79c0d2 - Deploying to gh-pages from @ 0b74d1c5f68fa5f8680ea2c724c166c9f6af6c8b 🚀
<_whitenotifier-e> [amaranth] whitequark edited issue #324: Integrate the CXXSim simulator - https://git.io/JDGSk
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<_whitenotifier-e> [amaranth] Ravenslofty commented on issue #592: Fragment.get should detect cycles in elaboration - https://git.io/JDGHS
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<d1b2> <TiltMeSenpai> hmm how does the irc - matrix bridge work? This channel doesn't show up in Element yet for me 😦
<sorear> if you join the room ID #amaranth-lang:libera.chat , the bridge will pick this up and automatically start bridging if it hasn't already
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<tiltmesenpai[m]> there we go i think?
<tiltmesenpai[m]> ayy hello world
<sorear> o/
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<esden[m]> how many different ways can I be in here? :D
<d1b2> <esden> heh... neat 😄
<_whitenotifier-e> [amaranth-boards] TomKeddie commented on pull request #146: butterstick: add board defn for r1.0 - https://git.io/JDZTw
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<_whitenotifier-e> [amaranth] jreyesr commented on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JDZrB
<cr1901> >They both work fine when paired with some quality-of-life changes I intend to submit after this PR is merged.
<cr1901> Somehow I still have those quality-of-life changes
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<Degi> Can I change to amaranth by replacing all imports and other mentions with amaranth?
<tpw_rules> i believe so?
<d1b2> <esden> The only difference I found porting the icebreaker examples was the fact that back.pysim is depricated and is now part of core amaranth. But I bet this happened already a while ago and has nothing to do with the rename. I just did not update the examples since a while. Otherwise all I had to do was just a simple :$s/nmigen/amaranth/g 😄
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