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<_whitenotifier-8>
[amaranth] jeremyherbert commented on issue #675: Add option to export only standards compliant VCD - https://git.io/JS1GB
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<d1b2>
<widlarizer> so the TLDR on Records is "unstable feature, probably don't use them"?
<d1b2>
<dragonmux> Records are a deprecated feature - use them if you need them but know they are going away and the replacement hasn't yet been written
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<d1b2>
<widlarizer> I wouldn't mind having little a spaghetti, but a guy in my comp arch class wrote his superscalar RV32I with clean records sequentially passed between stages in VHDL, and I feel bad about being beaten in readability by VHDL!
<d1b2>
<widlarizer> I still think Amaranth is really neat, though.
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<Guest59>
Hey there! Is it possible to instantiate a verilog module inside an amaranth design? I have an external IP block (in verilog) that I would like to reuse, but I haven't been able to find a way to instantiate that within the amaranth module hierarchy.
<Guest59>
I'd like to use the amaranth board definitions and build system so simply generating verilog and combining them manually afterwards doesn't feel like the way to go.
<adamgreig[m]>
both need updating to say "amaranth" instead of "nmigen"
<Guest59>
Great thanks! This looks exactly like what I needed!
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<_whitenotifier-8>
[amaranth] thirtythreeforty opened issue #676: Tip-of-tree amaranth not compatible with tip of amaranth-boards - https://git.io/JSDCH
<_whitenotifier-8>
[amaranth] thirtythreeforty commented on issue #676: Tip-of-tree amaranth not compatible with tip of amaranth-boards - https://git.io/JSDCQ
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<d1b2>
<widlarizer> is amaranth-yosys behind yosys? I want to try CXXRTL again, but am missing the hierarchy command in yosys