<d1b2>
<twam> I'm playing with lambdasoc and Minerva to run a custom RISCV in my designs. I load the code during compilation into a SRAMPeripheral (https://github.com/lambdaconcept/lambdasoc/blob/master/lambdasoc/periph/sram.py#L45) which sets the code as its init value. However recompiling the complete gateware for software changes is rather annoying and time consuming. Is there an easy way to inject the binary later into the bitstream?
<d1b2>
<zyp> you probably want the ecpbram tool (if targetting ecp5)
<d1b2>
<zyp> although for iterating even faster you might want to make the bram writable and just load right into it via a memory bridge in the fpga design itself
<_whitenotifier-8>
[amaranth-lang/amaranth-lang.github.io] whitequark bfb6f06 - Deploying to main from @ amaranth-lang/amaranth@c6dc08cbdda019cb8e902c17c03f682d89f603b9 🚀
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