16:27 <d1b2> <dave berkeley> I have an Instance() wrapping some VHDL code, and some Python test code that uses it. It seems to synthesise and run okay. I want to be able to generate CXXRTL code so I can test it. I've managed this in 3 runs of yosys : making a verilog file for the VHDL, then one for the Amaranth code, then combining both and generating CXXRTL cpp code. But I'm not sure if this is the right thing to do and I'm having trouble working out how to

16:27 <d1b2> access signals in the VHDL Instance. Are there any examples I could use for help?

18:49 <d1b2> <twam> I'm currently generating a SoC in my design which is roughly based on https://github.com/lambdaconcept/lambdasoc/blob/master/examples/minerva_soc.py. When build the top-class of design is instantiated (and constructors are run) files for building the software, e.g. automated include headers for the compiler are generated. Afterwards an external process builds the software. Only afterwards the platform.build() is executed. The problem I have

18:49 <d1b2> is that I need to move some parts of my design to being created in the constructors, so I can access them. For some things, this doesn't seem to be a problem, but if I want to access stuff which is defined by the platform, e.g. the clock frequency this doesn't work out. Is there a good way to work around this?