08:22 <d1b2> <dave berkeley> I've got a new (well, old) board working with Amaranth (blinky). It is a small Spartan-6 http://piswords.com/xc6slx16.html It is the same chip I need for work, so I bought the board to experiment on. It was pretty straightforward to create the Platform class, based on other similar Spartan-6 classes, using ISE on the command line. I also have it programming with a Digilent JTAG-HS3 adapter using openocd - again, based on similar

08:22 <d1b2> platform files in the amaranth-boards repo. It is not complete yet and I haven't worked out how to flash the SPI flash to make the bitstream persistent yet. Should I submit the platform to the amaranth repo? There is a full schematic on the manufacturer's site - zipped with their example code. I'm a bit hazy about the practice of adding toolchain_program() to the platform class, when my JTAG interface is not a standard thing. I also could do with

08:22 <d1b2> some pointers on how to flash the SPI chip. Should I be looking at a bootloader? The board has an FTDI-like USB UART interface (CH340C).

09:33 <d1b2> <dragonmux> board platforms are as far as we know always welcome

09:34 <d1b2> <dragonmux> as for the SPI Flash - you can hold the FPGA in reset and use any tool capable of talking SPI Flash to write the bitstream yourself

09:34 <d1b2> <dragonmux> the correct thing to write is the .bin starting at the 0th address in the device

09:35 <d1b2> <dragonmux> (holding in reset is a very important step as that causes the FPGA to high-Z its config pins and allows access to the flash)

09:44 <d1b2> <dave berkeley> The SPI flash pins aren't exposed on headers. Not sure how I can connect to them. I suppose I could JTAG program the FPGA to link the SPI flash pins to the connector and then connect to it through the FPGA?

09:45 <d1b2> <dragonmux> if you have a suitable JTAG dongle, that'd work

09:47 <d1b2> <dave berkeley> So I could have a simple FPGA image that connects the SpI flash to the connector (I can solder a PMOD header to it). Then use a SPI FTDI device to talk to the flash, via the FPGA, and program it from my PC. I have pyftdi working with a SPI interface, so I can just flash the chip using that?

09:51 <miek> both iMPACT and openFPGALoader (https://github.com/trabucayre/openFPGALoader) support programming attached flash over JTAG

09:51 <d1b2> <dave berkeley> Thanks. That's really useful.

10:00 <d1b2> <dave berkeley> That programs okay. Now to work out how to reach the SPI.

10:14 <d1b2> <dave berkeley> It looks like the openFPGALoader might use a similar trick to what I suggested above. My install has spiOverJtag_xc6slx100fgg484.bit and spiOverJtag_xc6slx45csg324.bit but nothing for the xc6slx16 I have.

10:24 <trabucayre> d1b2: could you provides exact/complete xc6 model ?

10:24 <d1b2> <dave berkeley> device = "xc6slx16" package = "ftg256" speed = "3"

10:26 <d1b2> <dave berkeley> It looks like I'd need to add a *.ucf file for this FPGA to the openFPGALoader code. Then generate a bitstream to give access to the SPI lines via the JTAG port. I think that is what it is doing.

10:26 <d1b2> <dave berkeley> This is all new to me.

10:28 <trabucayre> yep

10:28 <trabucayre> I need the ucf

10:29 <d1b2> <dave berkeley> I've added the SPI part to the amaranth platform file, but I haven't tried accessing it yet. I guess I could add something in my python that connects to those pins and it will generate the bits of UCF for me.

10:31 <d1b2> <dave berkeley> Or just type in the pins ...

10:33 <trabucayre> could you provides SPI pin mapping please ?

10:37 <d1b2> <dave berkeley> The W(rite protect) and HOLD pins of the SPI chip are pulled hi and have no connection to the FPGA.

10:37 <d1b2> <dave berkeley> *SPIFlashResources(0, cs_n="T3", clk="R11", copi="T10", cipo="P10", attrs=Attrs(IOSTANDARD="LVCMOS33") ),

10:38 <d1b2> <dave berkeley> I've not checked this yet. I just typed in the pins from the schematic.

10:39 <d1b2> <dave berkeley> spi_dout == P10, spi_in = T10. I'm not confident that I have these the right way round.

10:41 <d1b2> <dave berkeley> https://cdn.discordapp.com/attachments/726185180599156796/931860537782992976/scr_20220115104021.png

10:42 <d1b2> <dave berkeley> I'm assuming copi==spi_in but not sure.

10:45 <d1b2> <dave berkeley> So I guess each FPGA / package will boot from specific pins, so manufacturers have to use these for flash. So this config will be the same for all xc6slx16/ftg256 devices? Therefore this file can be used by other people using the same FPGA, but on different boards.

10:49 <trabucayre> https://github.com/trabucayre/openFPGALoader/commit/6597dcf374332d14cc98af8389f661c162c50f74

10:50 <trabucayre> as far I know SPI pins are package related

10:51 <trabucayre> but it's required to build all combinaison between package and size :-/

10:56 <d1b2> <dave berkeley> That is great. I'll have to get the latest. Not sure how I specify the spi bitstream on the command line.

10:59 <trabucayre> openFPGALoader --fpga-part xc6slx16ftg256

11:00 <d1b2> <dave berkeley> thanks. Just trying to build it ...

11:03 <d1b2> <dave berkeley> That works! Thank you so much.

11:20 <trabucayre> great!

11:23 <d1b2> <dave berkeley> I may have another package / pinout (csg324) for the same FPGA with a different footprint, but I will look at what you did and try and make a pull request. Might be a few days.

11:25 <trabucayre> ucf for xc6s csg324 is available

11:25 <trabucayre> so you have to update Makefile and build.py

11:28 <d1b2> <dave berkeley> thanks