00:23 <_whitenotifier-8> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JSZOk

00:23 <_whitenotifier-8> [YoWASP/nextpnr] whitequark 59a9d55 - Update dependencies.

00:47 <agg> I'm making an n-long Signal `s` and then write m.d.sync += s.eq(Cat(s[1:], s[0])) to form a shift register, but it seems to use 2n FFs in this ecp5, anyone have any ideas?

00:48 <agg> maybe it's an ecp5 thing and one ff in a slice can't feed the other or something but as far as I can tell the amaranth and the generated verilog look reasonable (i.e. the verilog has a single reg that's `n` long)

00:50 <whitequark> which toolchain?

00:51 <agg> yosys, nextpnr

00:51 <agg> haven't tried with diamond

00:51 <whitequark> does yosys do shift register inference on any of the supported architectures other than gp4?

00:52 <agg> I don't recall seeing it infer a shift register for ecp5 before, so I'm not sure, but I'd be happy with it just wiring all the FFs in series (I just want a long ff chain)

00:53 <whitequark> oh, I see

00:53 <agg> I'm not parallel loading it, but I do have a non-zero initial value for the bits (specifically I'm resetting to 01010101...)

00:58 <whitequark> generates `n` FFs here; can you post a reproducer?

01:00 <agg> hopefully, let me extract it (thanks for checking!)

01:01 <whitequark> hold on

01:01 <whitequark> so nextpnr packs 32 FFs into 16 TRELLIS_SLICEs

01:02 <agg> right, I'm getting n SLICE and 2n "TOtal DFFs"

01:02 <whitequark> but there are 16 TRELLIS_FFs in the synthesis results

01:07 <mwk> whitequark: it does shift register inference for xilinx fwiw, but it's not that useful as it has no reset support

01:08 <whitequark> yeah

01:08 <whitequark> agg:

01:09 <whitequark> agg: https://github.com/YosysHQ/nextpnr/blob/3266c51d853bfab6d890739010eb34fdc0fc38c7/ecp5/pack.cc#L87-L88

01:09 <agg> huh

01:10 <agg> so is it just using n SLICEs, one FF per slice, and reporting that as 2n FFs used because technically they are used up?

01:15 <agg> it looks like it is doing exactly that, if I push n beyond the number of slices in the device it uses about 95% of all slices, still reports 2n FFs used

01:19 <agg> Info: Total DFFs: 40000/24288 164% 🤔

01:30 <agg> well anyway I guess that resolves it, thanks!

01:31 <whitequark> I'm thinking it should be able to pack it to n/2 SLICEs

01:31 <whitequark> but I can't tell why it doesn't

01:32 <agg> it seems like it just doesn't bother if it doesn't need to

01:32 <agg> once I use all the slices it packs the remaining FFs into already-used slices

01:32 <whitequark> ah

01:33 <agg> but then reports 2n FFs used anyway, which is now >100% of available FFs

02:04 <_whitenotifier-8> [amaranth] modwizcode opened issue #673: [RFC] Support `bytes` in `Value.cast` - https://git.io/JSnzv

05:54 <_whitenotifier-8> [amaranth] jeremyherbert opened issue #674: Add more granularity to VCD export - https://git.io/JS0Q0

07:32 <_whitenotifier-8> [amaranth] modwizcode commented on issue #674: Add more granularity to VCD export - https://git.io/JSzFc

08:24 <RndMnkIII> Hi, happy New Year, I''m new to Amaranth coming from Verilog world

08:24 <whitequark> hi RndMnkIII!

10:29 <_whitenotifier-8> [amaranth] jeremyherbert commented on issue #674: Add more granularity to VCD export - https://git.io/JSaS4

22:24 <_whitenotifier-8> [amaranth] jeremyherbert opened issue #675: Add option to export only standards compliant VCD - https://git.io/JSi1y

22:31 <_whitenotifier-8> [amaranth] whitequark commented on issue #675: Add option to export only standards compliant VCD - https://git.io/JSiM2

22:36 <_whitenotifier-8> [amaranth] jeremyherbert commented on issue #675: Add option to export only standards compliant VCD - https://git.io/JSiDf

22:56 <_whitenotifier-8> [amaranth] whitequark commented on issue #675: Add option to export only standards compliant VCD - https://git.io/JSiSZ

22:56 <_whitenotifier-8> [amaranth] whitequark closed issue #675: Add option to export only standards compliant VCD - https://git.io/JSi1y