00:22 <_whitenotifier-e> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/nextpnr/compare/569697d4d0b9...b6f7650277a1

00:22 <_whitenotifier-e> [YoWASP/nextpnr] whitequark b6f7650 - Update dependencies.

01:28 <stevenjl> Hi all! Anyone fancy helping a rookie out? I'd like to communicate with an input/output bus attached to my Artix 7 but I haven't found any examples of switching between input / output for some Signal connections. I found https://github.com/amaranth-lang/amaranth/blob/main/amaranth/compat/fhdl/specials.py#L34 but it's in compat/fhdl so I assume

01:28 <stevenjl> there is a preferred alternative?

01:30 <adamgreig[m]> stevenjl: the Resource on your Platform should have dir="io", and then you'll get an object that has `.i`, `.o`, and `.oe` signal attributes

01:31 <adamgreig[m]> you can read from `.i` all the time, drive `.o`, and whenever `.oe` is asserted/1, the output is driven to the line

01:31 <adamgreig[m]> use that right at the device edge, and inside your logic, use separate signals for i, o, and oe

01:31 <stevenjl> aha, thanks!

01:32 <adamgreig[m]> (for example for an open-drain bus, set `.o` to 0 always, and use `.oe` to control whether it's driven to 0 or high-z)

01:33 <adamgreig[m]> you can't (generally speaking) have a tristate wire inside the fpga - it's always an input or an output, so best to represent that as separate i, o, oe signals, that eventually feed the special IO hardware block that has a tristate driver

01:35 <stevenjl> Got it

01:36 <stevenjl> so adding Resource("SomeName", 0, Pins("H8", dir="io")) in my board class would be an example for a single pin

01:37 <stevenjl> which I can retrieve as x=platform.request("SomeName") and I can use the x.o, x.oe x.i just like any Signal?

01:39 <stevenjl> And I guess I can do Resource("SomeName", 0, Pins("H8 XX YY ZZ", dir="io")) for 'bus' with some width?

01:39 <adamgreig[m]> yep, exactly so

01:39 <stevenjl> Perfect, thanks so much!

07:04 <d1b2> <Hardkrash> @sarayan When designing for the from your_module import * the __all__ special variable is a good thing to implement. See this documentation. https://docs.python.org/3/tutorial/modules.html#importing-from-a-package

08:49 <Sarayan> d1b2: thanks

08:50 <Sarayan> Yep, sounds like a very good idea

08:50 <cr1901> FWIW, d1b2 is the Discord bridge, I think you meant to thank Hardkrash

08:51 <Sarayan> Hardkrash: what I said :-)

08:51 <Sarayan> indeed I did

08:52 <cr1901> I mean, you can thank both! I just don't think d1b2 will feel the gratification :(.

08:54 <Sarayan> Well, whitequark was saying she knows people arguing thermostats could be considered concious, so... :-)

08:59 <Sarayan> conscious

09:53 <lethalbit> has anyone designed an amaranth mascot yet? i feel as is it needs a cute mascot

09:53 <lethalbit> (i would but my artistic skills are on part with a potato)

09:54 <lethalbit> Maybe wq could ask Tyson Tan, they did the Krita mascot

11:00 <whitequark> I'll consider it!

11:08 <lethalbit> =^w^=

19:25 <key2> is it possible to have an FSM inside another FSM?

20:01 <d1b2> <Herr Brain> That is how every large digital system is implemented.

20:01 <whitequark> yeah

20:43 <d1b2> <esden> state machines all the way down 🙂

20:57 <d1b2> <Conventia> I suppose it depends on how you define 'inside'... if you're being pedantic. 😛

20:57 <d1b2> <TheManiacalLemon> I would assume it means using nested with m.FSM():

21:00 <d1b2> <Conventia> I haven't actually used amaranth yet. I was mostly just making a joke about some hardware being inside other hardware, when that's impossible, even though that's conceptually what people think.

21:00 <d1b2> <Herr Brain> Or up, depending on your perspective.

21:01 <d1b2> <Conventia> But yes, state machines aren't particularly useful if you're only allowed one, in general.

21:04 <Sarayan> ya dawg, I heard you liked state machines