<electronic_eel>
azonenberg: have a look at figure 8-12 of the buf802 ds. it shows a different internal architecture than figure 8-1 regarding in_aux
* azonenberg
looks
<electronic_eel>
unfortunately i don't really see a method to increase offset compensation with that one
<electronic_eel>
i'm wondering how the dc offset works in cl mode
<azonenberg>
yeah so the question is how to fix this
<electronic_eel>
the additional opamp can't do magic, it has to work through the in_aux pin
<azonenberg>
Yeah but there's an important difference
<azonenberg>
in full CL mode there is no dc bias at the IN pin from the source signal
<azonenberg>
it's ac coupled and biased through IN_BIAS
<azonenberg>
having a dc component at IN might be causing the problem
<azonenberg>
as it might lead to a static current through the input jfet that is too large to null out
<azonenberg>
via in_aux
<electronic_eel>
yeah, that might be the case
<azonenberg>
anyway, so paths forward
<azonenberg>
all attempts at using fake CL mode with dc coupled input have been unsuccessful
<azonenberg>
so i think we can eliminate that as an option
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<electronic_eel>
could you abuse the in_bias pin for offset comp?
<electronic_eel>
or is the internal 100k too high for it to be effective?
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<azonenberg>
um, if anything i'd be worried about it being too *low* :p
<azonenberg>
that's an interesting idea , it's connected to the same point in the circuit as the Vbias BJT
<azonenberg>
so i could plausibly inject a sink current into that maybe? but it's iffy
<azonenberg>
anyway, thinking back at a higher level vs specifics of the buf802 for a second
<azonenberg>
v0.2 AV1 injects the nulling voltage into IN via a 1M resistor
<azonenberg>
more precisely, the 1M ohm "terminator" at the input is actually tied to a pot
<azonenberg>
so you can terminate to a voltage slightly off ground, thus nulling out the output offset
<azonenberg>
the problem is you backfeed this termination voltage (through 5M ohm ESR) into the input
<azonenberg>
and when the input floats / has more than a few megohms source impedance, you get wrong offset at the output
<azonenberg>
So i think this approach is probably not good long term
<azonenberg>
essentially i'm doing figure 8-11 but without C1
<azonenberg>
and a pot instead of an opamp driving the R1/R2 node so all of the feedback circuit etc can be eliminated
<azonenberg>
so we just have R1 directly to the pot wiper
<azonenberg>
it works great, minus the problem of having bias fed back into the input
<azonenberg>
So i think that's also a no-go
<azonenberg>
at this point i see two primary paths forward
<electronic_eel>
i concur. you use an active probe when you want to minimize all effects on the dut
<azonenberg>
the first is to go full CL mode
<azonenberg>
see figure 8-12
<azonenberg>
if we choose the sum of the alpha network to equal 1M ohms
<azonenberg>
that can be our 1M terminator for the input toe ground
<azonenberg>
the 330 pF series cap appears in series with the 2.4 pF amplifier input cap, but is so much larger than the 2.4 that the effective input capacitance is substantialyl unchanged (it comes out to 2.38 pF, within any reasonable tolerance bound of insignificant)
<azonenberg>
so we should not need any change to the input compensation structure i think
<azonenberg>
just might need 1-2 fF more/less on the trim cap. trivial to tune
<azonenberg>
the current drawn by the precision amp should be negligible compared to the 1M ohm of the alpha
<azonenberg>
and in fact, 1M is the recommended value in their figure 9-1 example
<azonenberg>
The advantage of this is that the OPA140 or equivalent is a low BW amplifier so probably does not consume a lot of power
<azonenberg>
we'd need to find an equivalent as last i checked OPA140 is unobtainium and it also comes in fairly large packages like soic8
<azonenberg>
which are no good for active probes :p
<azonenberg>
ideally i'd like WLCSP
<azonenberg>
failing that, UQFN/DFN
<azonenberg>
anyway, looking at all of the support circuitry it seems like the figure 9-1 design, minus the 50 ohm terminator, should be OK? in terms of not unduly loading the DUT
<azonenberg>
and working OK with our existing capacitive divider design
<azonenberg>
it's just going to cost us a fair bit of board area. we're looking at an amplifier, six resistors, three caps, plus decoupling for the amplifier itself
<azonenberg>
The other option I see is to keep the input untouched, have a static offset on the buf802 output
<azonenberg>
then have a garden variety opamp at the output with a nulling voltage at the inverting input
<azonenberg>
advantage: this allows us to apply gain to make up for some of the 10x attenuation of the probe
<azonenberg>
disadvantage: we now need a GHz bandwidth single ended amplifier at the output. those are hard to find and power hungry
<electronic_eel>
from the points you wrote, the cl option looks better to me. downside is that all the smaller packages for the opa140 / opa2140 seem to be hard to get and have a lead time sometime in 2023
<azonenberg>
Yes. So i think the best option is to use CL mode but swap the OPA140 out with something else
<azonenberg>
OPA210 is SOT23-5
<azonenberg>
Ti has nothing smaller in the "precision" category
<azonenberg>
LT6003?
<azonenberg>
comes in 2x2mm DFN
<electronic_eel>
wow, the opa210 in sot-23 seems to be in stock
<azonenberg>
(havent checked stock on it yet)
<azonenberg>
digikey has them
<azonenberg>
568 in stock for $2.72 a pop
<electronic_eel>
the LT6003 seems to have a too low gpb with 2 kHz. the crossover-region for the cl mode goes into the lowish mhz region
<azonenberg>
and i was about to rule it out for noise anyway
<azonenberg>
ADA4075-2?
<azonenberg>
2.8 nV/rtHz noise, 6.5 MHz, can run on +/- 4.5V dual supply which is what i'm using, 2x2mm 8-lead DFN
<azonenberg>
we need a gain of about 4 if i'm reading the buf802 datasheet right
<azonenberg>
which means we can work out to 1.5ish mhz?
<azonenberg>
that should be OK for the crossover in CL mode?
<electronic_eel>
could be a bit tight, but might work
<azonenberg>
it's small and i can actually get it
<azonenberg>
so that counts for a lot :p
<azonenberg>
digikey has a full reel of 3k in stock now
<azonenberg>
supply current of 3ish mA is negligible compared to the rest of the board
<electronic_eel>
you could make two layouts, one with opa210 in sot23 and one with ADA4075-2. then compare performance
<azonenberg>
i'm inclined to just do the ada4075 on the next spin, but i'll order some opa210s in case i change my mind
<azonenberg>
Ordered ten of each
<azonenberg>
anyway i think i'm gonna try to finish the board design today and get everything ordered. with the holiday weekend i dont expect to get parts or anything for a while though
<electronic_eel>
at least the opa210 has the classic text in the datasheet that the input voltage might go above supply if the current is limited to 10 mA. with more than 4 meg at the input this should allow quite high dc voltages before damage occurs
<electronic_eel>
i know it is designed as solder-in probe, but mistakes can still be made...
<azonenberg>
its not just 4M it's 4M / 1M divider
<azonenberg>
supply is 4.5V so rail-to-rail as seen by the amplifier is over 20V
<azonenberg>
i'll worry about exact absolute max ratings for the datasheet etc later
<azonenberg>
also if i am successful with the solder in variant
<azonenberg>
i do want to explore a handheld version eventually
<electronic_eel>
the divider is relevant for the voltage you get on the opamp in. but when you use the 10 mA limit clause in the datasheet, it is just the resistance in the path that matters
<azonenberg>
yeah there's that
<azonenberg>
my point is more, it takes a pretty high voltage before we even hit the max in the first palce
<azonenberg>
place*
<azonenberg>
much less current limits
<azonenberg>
we're below the rails and fully in spec
<electronic_eel>
define "pretty high voltage". i think about something like a 48v power rail or similar
<azonenberg>
you dont need a GHz probe for that
<azonenberg>
"pretty high" meaning way outside what you would use a typical active fet probe for
<electronic_eel>
no, but you might accidently pick the wrong pin
<azonenberg>
there is that. but in typical high density digital type stuff you don't have anything past 12V intermediate rails
<azonenberg>
if anything is higher it's in a dedicated part of the board for big DC-DC modules
<azonenberg>
for reference the ZS1500 is +/- 8V dynamic range and 20V non-destruct voltage
<electronic_eel>
yeah. but it could be easier to solder the probe to a connector than to an ic. and the connector could have power and signals next to each other
<azonenberg>
that's the kind of range i was targeting
<azonenberg>
20V absolute max would imo be totally reasonable as a spec
<azonenberg>
in any case, i am not designing for a specific max voltage
<azonenberg>
i'm designing for the highest bandwidth and lowest loading i can get in a high impedance single ended probe
<azonenberg>
and will then figure out how much voltage i can throw at it when i'm happy with the other specs :)
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<josuah>
how does one measure the current on an ASIC, if that ever is possible?
<josuah>
only through simulation? via the existing pads (like the +3.3v, the various GND, the GPIOs, etc.)? Are there such things as ASICs testpoints (routed to larger areas to put a wire to)?
<josuah>
maybe the thing is: when it in the form of a taped out ASIC, it is too late alrady...
<josuah>
instead of current, I mean signal and more generally electrical properties
<azonenberg>
asic test points exist, and are normally used both for verification of design during R&D and for production line test of individual chips
<azonenberg>
Depending on the application, sometimes they are full sized bond pads that have standard i/o cells on them
<azonenberg>
and just aren't bonded out in the final package
<azonenberg>
sometimes they *are* bonded out and are just listed as NC or DNU in the datasheet
<azonenberg>
you can see the big squares around the perimeter with the circular damage on them where bond wires were ripped off during decap
<azonenberg>
there's also additional large square bond pads with no damage, these are for different pin count packages (I think this was packaged in a 32-pin package but they have a 56 ball BGA too)
<azonenberg>
so those pins weren't bonded on this particular die
<azonenberg>
but you'll also notice six more pads that are slightly smaller and rounded vs the others
<josuah>
a few monthes ago, I thought that I would never be able to tell what anything from these chips could map to
<d1b2>
<bob_twinkles> I think there's some work toward getting curves back in chips, especially as be blaze right past single-pattern EUV into complex multipaterning stuff
<d1b2>
<bob_twinkles> since you need to do all the hard modeling anyway, you can get curves back and improve manufacturability at the same time
<azonenberg>
oh? i'm seeing the opposite, some masks are essentially becoming 1D
<azonenberg>
where you have e.g. poly being restricted to parallel lines at regular intervals over the whole hcip
<azonenberg>
then you have a second mask to cut the lines into separate collinear pieces
<azonenberg>
this is based on what i've seen on 28nm though. i haven't seen any inside details of newer processes