sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<palmer> I got a cold on the plane, so I'm going to be kind of out of it today and probably no PR tomorrow
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<conchuod> I see Krste has a new amazing idea
<conchuod> I'm looking at his most recent suggestion for how his "Moving SBI functions out of M-mode using (H)S-mode dynamic linking" would work
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<conchuod> and it seems to resemble what is already being done when sbi/ecall stuff has been replaced by code running in s-mode instead
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<sorear> link?
<sorear> "dynamic linking code into S-mode" sounds like somebody just reinvented UEFI, probably even worse
<sorear> (runtime services)
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<jrtc27> if it's fancy enough to need abstracting like that, it probably belongs in UEFI or ACPI
<jrtc27> if it's not then the OS can do it directly
<jrtc27> and if you need to call to M/HS-mode, do an ECALL
<jrtc27> that's the sane approach taken by any other architecture
<jrtc27> (ignoring OpenFirmware)
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<jrtc27> and maybe don't design a shit ISA in the first place that requires M-mode calls for things that S-mode should be able to program directly
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<jrtc27> that's the only real reason it even seems appealing
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<sorear> sbi 1.0 is a ratified spec and thus according to the 201x promises must be supported for 50 years, stop trying to set single-digit removal schedules for rfence et al
<sorear> "IMSIC means we don't need rfence" is a non-sequitur in at least three ways (there is a binding compatibility promise; you can emulate rfence with any IPI scheme, not just IMSIC; the documented purpose of rfence is to support broadcast invalidation hardware like c910 has, which IMSIC is not an improvement on)
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<sorear> (do any of you know if broadcast invalidation/fences works on the sg2042?)
<jrtc27> given they couldn't even get TLBs right...
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<muurkha> interesting, thanks for the link, sorear