sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<sevan> a while back I reported that the LicheeRV running Ubuntu struggled with time issues resulting in clock drift being reported when you invoked ping for example. That was the case on 22.10 and 23.04 with 5.9 kernel. I'm pleased to say now that the 6.2 kernel has landed in 23.04, the issue no longer appears. I forget who responded here at the time, but thanks either ways.
<Esmil> sevan: Nice! Thanks for letting me know
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<muurkha> oh no, the T-Head cores have a bug in their float underflow support?
<Esmil> i don't know any more than what is in that thread, but it looks like it yes
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<sorear> appears to only affect flags generation, and only in the case where an underflow rounds to the smallest *normal* number
<muurkha> so it generates the correct flags when it underflows further and denormalizes?
<sorear> probably less impactful than the FENCE bug, although harder to work around; wonder if this or the fence bug is fixed in c908
<sorear> i assume so since nothing with an exponent of +00 appears in the comments
<Esmil> sorear: what the FENCE bug?
<Esmil> *what is
<sorear> c906 and c910 generate spurious illegal instruction exceptions if the "ignored by hardware, software must set 0" fields in FENCE are not zero
<muurkha> my knowledge of gradual underflow is pretty minimal, so I don't have a good way of estimating how important this is
<sorear> one of those encodings was used for FENCE.TSO
<sorear> opensbi has a workaround in the illegal instruction handler
<Esmil> ah, so for that one software that "behaves" shouldn't see it, but it's still a hardware bug since it doesn't do what the spec says?
<sorear> it's a forward compatibility issue that became a real issue when the spec was revizsed
<Esmil> right
<muurkha> well, if you can work around it in the illegal instruction handler, it's "just" a performance bug?
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<muurkha> in this case you don't have that option; there's no exception to handle
<muurkha> right?
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<sorear> riscv loves sending mixed messages on whether conformance requirements are binding in M-mode
<sorear> a S-mode workaround is possible here by leaving sstatus.FS=0 and emulating floating point, although the perf cost is dreadful
<sorear> (misa.F write support should have been mandatory)
<mwette> Is this best place to start w/ VisionFive2 board/box? https://doc-en.rvspace.org/VisionFive2/SDK_Quick_Start_Guide/index.html (e.g., wrt SDK)
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<jrtc27> conformance test suite
<jrtc27> what's what
<jrtc27> *that
<jrtc27> who needs one of those