sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<aurel32> I have been trying to the use the cpufreq driver of the VF2, and the operation points seem to assume a 1.5 GHz maximum frequency, while in practice to be 1 GHz corresponding to the frequency of PLL0
<aurel32> so that means message like: cpufreq: cpufreq_online: CPU0: Running at unlisted initial frequency: 1000000 KHz, changing to: 1500000 KHz
<aurel32> plus the chosen value is different from the requested one
<aurel32> Does someone know how to change the PLL0 output frequency, and if it safe to run the CPU at that frequency?
<la_mettrie> in a file drivers/clk/starfive/clk-starfive-jh7110-gen.c there is a call clk_set_rate(pll0_clk, PLL0_DEFAULT_FREQ)
<la_mettrie> this second (and last) argument is the value for pll0 freq
<la_mettrie> i actually don't know why (and if it's peculiar) it is set in a manner that bypasses other functionality of the clk driver
<aurel32> hmm i don't have this file (looking at linux-next)
<aurel32> i have found the code to read the value, but not set it
<la_mettrie> you are probably looking at the mainline linux repository while the file is from starfive's own github that they use (i think) for their sd images
<aurel32> yep i am using mainline linux and the cpufreq driver also comes from there
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<leah2> anyone seen such a build failure with gcc 13.2? https://l2.re/FUiDA7
<leah2> using --with-arch=rv64imafdc --with-abi=lp64d which should be a default config?
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<Tenkawa> whew.. fixed my initramfs issue
<Tenkawa> leah2: are you cross compiling from x86_64?
<leah2> yes
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<leah2> 11.2 works but i need new patches that are in 13
<Tenkawa> hmm.. I just found a possibility.. let me read it just a sec
<Tenkawa> The post I found doesn't seem relevant
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<Tenkawa> ooh
<Tenkawa> nice
<aurel32> Esmil: oh I missed that, I'll try it asap
<aurel32> oh it was not sent on the list, that's why I missed it
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<Esmil> aurel32: yeah, i only noticed because i was cc'ed
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<aurel32> i guess that can give a significant performance boost and put the vf2 way ahead the unmatched
<Esmil> aurel32: it's already way ahead of the unmatched just because it's a later revision of the sifive cores where they fixed some memory bandwith issues
<aurel32> yes, it's already ahead, around 20% for the cases i have looked at
<Tenkawa> Can that one be applied to the 6.5-rc kernel? or is it newer than that?
<aurel32> yes, i have applied on a 6.5-rc7 kernel, currently building
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<Tenkawa> Nice.. let me know if it works, I want to throw that in if it does
<Esmil> Tenkawa: it works fine. i'm just not sure it's the right way to do it
<Tenkawa> Oh. whats the concern?
<Esmil> That it hardcodes setting the PLL0 rate to 1.5GHz in the driver
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<Tenkawa> ahh.. no flexibility
<Tenkawa> It could be coming in from the dts at a different speed right?
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<mps> u-boot file drivers/clk/starfive/clk-jh7110-pll.c have interesting static const struct starfive_pllx_rate jh7110_pll0_tbl
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<aurel32> Tenkawa: i confirm that it works fine
<aurel32> i get around 40% performance increase from the first measurements
<Tenkawa> excellent
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<mps> how do you benchmark cpu speed? would like to test now and after applying above patch
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<aurel32> mps: in my case building a package
<Tenkawa> recompiling the kernel felt faster
<mps> this adds i/o to the equation. in meantime I hacked simple one line bash script and 'time' command to get some results
<mps> now building kernel and will check tomorrow
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