<sorear>
this isn't the first version of the spec but I'm too tired to look for it
<jrtc27>
I'm being slightly facetious, I remember seeing stuff years ago
<jrtc27>
but that link is the first I'm hearing of anything happening in the past couple of years
<jrtc27>
odd to be doing it by circulating pdfs of word documents on mailing lists rather than putting stuff in the repo though
<sorear>
i need to pick holes in that later, i don't think it's going in a useful direction
<courmisch>
some people can't VCS
<jrtc27>
"Clean data to Point of Unification"
<jrtc27>
ah so now we're going from no-Arm to full-Arm
<courmisch>
that sounds like copy past from Arm ARM
<courmisch>
copy-paste*
<sorear>
"let's add new data cache flushing instructions to optimize fence.i on hardware with incoherent data caches" is not a direction that benefits any of the people currently having JIT problems
<jrtc27>
clean.id is unhelpful for SMP
<jrtc27>
oh
<jrtc27>
ew
<jrtc27>
their definition of PoU is different
<jrtc27>
"Point of Unification – the point bin the memory hierarchy where cached data can be fetched by the instruction fetching mechanism of any HART if all instruction caching (if present) is invalid."
<jrtc27>
that's not PoU, that's PoC...
* courmisch
facedesks
<gurki>
im not certain putting a desk in your face is a wise approach
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* gurki
runs
<jrtc27>
hm, although, PoU is for all IS in Arm, isn't it
<jrtc27>
which in practice means all PEs...
<Stat_headcrabed>
What kind of instruction is needed for SMP?
<jrtc27>
so I guess that is the same given RISC-V has no IS/OS distinction
<jrtc27>
(which is a waste of time; no OS supports outer shareable)
<courmisch>
well, no TLBI to OS, so yeah writing an OS would be painful
<jrtc27>
OS is really "there are some other cores over there you can run a separate OS on if you want"
<courmisch>
is there even an actual hardware that differentiate OSH and NSH?
<jrtc27>
not that I know of
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<courmisch>
hmm... shouldn't it be a pin on the CPU though? I should check the TRMs
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<courmisch>
Stat_headcrabed: I think the point is that there are no defined instructions for that case
<Stat_headcrabed>
I mean, what should the needed function do?
<courmisch>
flush the instruction cache across harts
<Stat_headcrabed>
Currently we use IPI + zifencei in linux?
<courmisch>
basically, we need Armv8's IC IVAU
<courmisch>
Stat_headcrabed: I guess
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<Stat_headcrabed>
Maybe we could ask J-spec group about this?
<jrtc27>
linux does it lazily
<jrtc27>
it'll IPI running threads, but any that aren't scheduled will instead have a flag set so they get a fence.i when they're next scheduled
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<jrtc27>
uh, amend that to: it'll IPI harts running threads from that process, but any that are doing something else will have a flag set so they get a fence.i when that process is next scheduled on them
<sorear>
c910 has hardware support for a broadcast fence.i but it's kinda weirdly exposed
<Stat_headcrabed>
And it's not efficient enough?
<jrtc27>
for single-threaded things it's probably not awful
<jrtc27>
for multi-threaded JITs it's awful
<Stat_headcrabed>
OK
<Stat_headcrabed>
thanks
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<jrtc27>
but IANA JIT dev (thank god)
<Stat_headcrabed>
Have you ever propose a issue to j-spec or email for this problem?
<heat>
jrtc27, can the CPU prefetch from non-executable memory?
<heat>
cuz, you know, I don't see the big issue with JITs there. you grab a new block of writable memory from mmap, JIT your things, mprotect PROT_EXEC it, done?
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<jrtc27>
it can
<jrtc27>
AFAIK
<jrtc27>
so long as the PMA says so (which it will, because it's memory)
<jrtc27>
but also, even if not, that's all well and good until you munmap and later mmap again
<jrtc27>
(which may be two totally different libraries)
<jrtc27>
although, I guess that needs to be made secure anyway
<jrtc27>
mmap gives zeroes so jumping to it should be well-defined
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<heat>
i dont know about riscv but x86 seems to be weirdly natively protected in that regard
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<courmisch>
wasn't there an attack exploiting that fence.i flushes the entirety of the I-cache?
<heat>
you don't need anything special in x86 between mmap/munmap PROT_EXEC
<courmisch>
I thought x86 was using IPI for that, but that could be dated or incorrect
<heat>
it uses IPI for cross modifying code, and for TLB shootdowns
<courmisch>
maybe not due to IC, but due to TLB
<heat>
does not use IPI for serialization across mmap
<heat>
it has been mentioned in the lkml before, it's some sort of thing that Just Works despite not being documented anywhere
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<oddcoder>
not sure if this is worth the discussion here, but I was reading through Risc-V isa Volume II and some naming conventions are very confusing.
<oddcoder>
in particular the fact that the supervisor OS runs in supervisor mode
<oddcoder>
while the Supervisor Execution Environment runs in machine Mode
<oddcoder>
My intution keeps telling me Supervisor OS runs in Supervisor Execution Environment, but apparently this is not how name selections was picked.
<oddcoder>
I am not sure if it makes any sense to request different names for things (perhaps calling SEE something else)
<oddcoder>
ofcourse that is assuming my understanding is correct.
<jrtc27>
machine mode provides the supervisor execution environment
<jrtc27>
the supervisor OS runs in supervisor mode in the supervisor execution environment
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<oddcoder>
it didnt' feel like it runs inside SEE, it felt like SEE offers ABI (the SBI) and that ABI is accessed by the OS via syscall like interface
<oddcoder>
which makes is sound like OS makes call into SEE rather than run inside it.
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<jrtc27>
hm, indeed, that's a strange way to define it
<jrtc27>
it starts off fine with "Each application communicates over an ABI with the OS, which provides the AEE."
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<jrtc27>
but "The SEE can be a simple boot loader and BIOS-style IO system in a low-end hardware platform, ..." is strange
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<oddcoder>
wait, so you are trying to tell me that it is not intended to be simple bootloader/BIOS ?
<oddcoder>
because that is the only usecase I had in mind, I am not sure if you meant to say that this is the strange case ? or did I misunderstand something
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<jrtc27>
the wording / definition
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<oddcoder>
do you think it would make sense to request name change (and where to make it) ? I mean BIOS will be much nicer name than SEE. At least everyone would understand what it is immediately.
<geist>
but it might not be a BIOS, which is why it's named that way. it could be provided by a hypervisor that is hosting the supervisor OS
<geist>
hence why it's generically named, its basically whatever is at the other end of the ecall into it
<oddcoder>
what would be the difference if it is provided by hypervisor? it will still be a interface for configuring Basic Input and Output?
<geist>
well, the SEE doesn't really provide basic io
<oddcoder>
Basic might mean different things when talking about different layers.
<geist>
its more of a cpu/system abstraction
<geist>
or maybe another way of putting it is it does more and less than what a traditional BIOS would, which is probably why calling it a BIOS would not be great, because it would imply a bunch of things it isn't
<oddcoder>
I will have to read more, the only issue I wanted to raise, is that SEE as a name with respect to what it does is confusing
<geist>
so it uses a really generic term to describe it
<geist>
i read it as this level of docs is implying that there *is* an enviroment that the supervisor OS calls into, without going into too much detail what its for or what it does
<geist>
since that's another document
<geist>
then when you get over to the other docs that describe the interface (SBI) you'll see it's not really a bootloader or a bios (except maybe the console routines) but more of a cpu/interrupt/timer abstraction
<jrtc27>
BIOS is a very specific thing
<oddcoder>
gesit: ofcourse you do because I suppose you are already familiar with the concept but for first time reading It was confusing, especially that every other ISA when they say XEE it mean X is running inside the environment.
<jrtc27>
even your x86 PC doesn't have a BIOS any more
<oddcoder>
jrtc27: you don't consider uefi as a BIOS?
<jrtc27>
no
<oddcoder>
I see your point, It is unlikely we are going to agree.
<jrtc27>
BIOS is what grew out of CP/M and then became the IBM PC BIOS
<jrtc27>
nothing else has ever been officially called a BIOS that I know of
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<jrtc27>
semi-tech-literate people will call UEFI firmware a BIOS, though
<jrtc27>
and QEMU unhelpfully uses -bios for firmware in general
<oddcoder>
qemu people will be delighed t hear about that
<oddcoder>
well it is not just qemu for the record, qemu and every software that runs on that level
<oddcoder>
I ammend my last statement, not every I will just say many software*
<oddcoder>
But this is not the point I am trying to make here,
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<muurkha>
"SEE" is a pretty terrible name for two reasons
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<muurkha>
- it's an existing, common English word
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<muurkha>
- even if it were obviously an acronym, it's only three letters, which means there are many existing expansions: Seeing Essential English, Signing Exact English, Society for Environment and Education, Special Enrollment Examination, standard error of the equation, southeast Europe, Square Enix Europe, small emplacement excavator, and dozens of lesser-known expansions
<geist>
SDOS - supervisor doer of stuff, or SHA - supervisor higher authority
<muurkha>
even another single letter would be helpful. I hesitate to suggest SEXxE but perhaps SEEn or SuEE,
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<muurkha>
SDOS would be maybe better; it even suggests that it's a primitive operating system
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<oddcoder>
geist: Sha exists elsewhere ... but SDOS is nicer than see because it force the reader to make no assumption