sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<Trigraph__> i am trying to understand why in push_off routine intena is saved, it is not used to restore interrupt flags in pop_off
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<Trigraph__> and why inena is checked in this line https://github.com/mit-pdos/xv6-riscv/blob/f5b93ef12f7159f74f80f94729ee4faabe42c360/kernel/spinlock.c#L108 it appears that if n_off = 0 then it is safe to enable interrupts
<sorear> unless something else disabled interrupts before the first push_off?
<Trigraph__> that's a great point i did not consider that interrupts could be disabled via calls except in push_off/push_on
<Trigraph__> looks like no other code invokes int_off though
<sorear> might be other things that write sstatus. if nothing else, the hardware always disables same-level interrupts when a trap is taken
<sorear> usertrap has an intr_on to counteract that for system calls but other traps might be processed with interrupts still disabled
<Trigraph__> i see, i am yet to go through the chapter which discusses privileged execution modes
<Trigraph__> i guess a status register read on exception by default returns interrupts as disabled unless they are explicitly enabled on user trap if i understand your explanation, let me try tht in qemu
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<sorear> chapter of what?
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<Trigraph__> The Risc V architecture Atlas
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<Trigraph__> Thank you for the explanation sorear
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