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<Trigraph>
i came across this section : "An interrupt i will be taken if bit i is set in both mip and mie, and if interrupts are globally enabled.
<Trigraph>
By default, M-mode interrupts are globally enabled if the hart’s current privilege mode is less than
<Trigraph>
M, or if the current privilege mode is M and the MIE bit in the mstatus register is set. If bit i
<Trigraph>
in mideleg is set, however, interrupts are considered to be globally enabled if the hart’s current
<Trigraph>
privilege mode equals the delegated privilege mode (S or U) and that mode’s interrupt enable bit
<Trigraph>
(SIE or UIE in mstatus) is set, or if the current privilege mode is less than the delegated privilege
<Trigraph>
mode."
<Trigraph>
Does this imply that when timer interrupts are routed to machine mode there is no need to set MTIE ?
<jrtc27>
depends if you want to take timer interrupts while you're in machine mode or only when in supervisor/user mode
<jrtc27>
oh
<jrtc27>
well MTIP takes effect regardless of what mode you're in
<Trigraph>
perhaps a hangover from arm days but i am confused by the use of term "globally enabled" in the above statement.
<jrtc27>
MIE in mstatus is like the I in DAIF
<jrtc27>
if that helps
<jrtc27>
"have you turned off all interrupts (likely because you're in a critical section)" vs "have you turned off this specific interrupt"
<Trigraph>
is the global enable controlled by some other bit in CSR's ?
<jrtc27>
that *is* the xIE bit
<Trigraph>
ah
<jrtc27>
xstatus.xIE: block or allow interrupts whilst executing in mode x
<jrtc27>
xie.y: block interrupt y
<jrtc27>
note that xIE is per-mode, whilst xie.y is shared across all modes (that have it delegated)
<jrtc27>
hence why the former only applies to mode x but the latter applies to all mode
<jrtc27>
*s
<Trigraph>
i was confused about a separate global enable because of the 'and' clause in this statement "An interrupt i will be taken if bit i is set in both mip and mie, and if interrupts are globally enabled"
<jrtc27>
so, RISC-V is unhelpful
<jrtc27>
mie there is the CSR "mie"
<jrtc27>
MIE earlier is the "MIE" bit in the CSR "mstatus"
<jrtc27>
if that's where the confusion came from
<Trigraph>
ah yes
<Trigraph>
let me re-read again to make sure i understand
<jrtc27>
i.e. "An interrupt i will be taken if bit i is set in both mip and mie" -> mip[i] & mie[i] != 0 ; "and if interrupts are globally enabled" -> mstatus.MIE != 0
<jrtc27>
well, mstatus.MIE != 0 || cur_priv < M
<Trigraph>
;)
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