sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<palmer> did we get around to documenting the whole "we use patchwork, and if the checks fail then your patch probably needs a respin" stuff in Linux land? IIRC I was talking with someone about writing that up at some point
<Armand> Things I'm glad I don't deal with ^ :P
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<pabs3> rory_be: what hardware/emulator are you doing riscv64be on?
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<conchuod> Probably with me at some point palmer
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<drmpeg> conchuod: Isn't there a third patch in that dtb series for stable?
<drmpeg> riscv: Do not set initial_boot_params to the linear address of the dtb
<drmpeg> Looks like it won't hurt if it's missing.
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<conchuod> Tbh, I hope Greg just drops the lot and tries again for the next time around drmpeg
<drmpeg> Agree.
<conchuod> A "normal" system boots fine with what he has picked, but I think the corner cases need all 3
<conchuod> Also, nobody has even tested XIP /shrug
<drmpeg> You got your wish.
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<conchuod> And Alex is saving me from doing the backports :)
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<conchuod> I still think it's not right though in -rc2..
<drmpeg> Yeah, that "riscv: Do not set initial_boot_params to the linear address of the dtb" patch got left in.
<drmpeg> It was there before, I just didn't scroll down enough in the git log.
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<Tenkawa> Well this appears to be working nicely
<Tenkawa> [ 0.000000] Linux version 6.2.11-vf2+ (root@vf2) (Debian clang version 14.0.6, Debian LLD 14.0.6) #17 SMP Wed Apr 19 00:14:45 EDT 2023
<Tenkawa> Took a while to build that kernel but it runs a full LTO kernel now on my VisionFive2
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<conchuod> Yah drmpeg, I replied to both 6.1 and 6.2 now. There's another commit from mmind00 that I think should be dropped too
<drmpeg> 6.1 actually bombs with that commit.
<drmpeg> I think. Testing the revert now.
<mmind00> conchuod: is this about these stable-patches I got mails yesterday about?
<conchuod> Yea
<conchuod> That's all dead code, the patch that depends on it has a custom backport do pulling yours back is not needed
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<palmer> I think I got everything cleared out from the patchwork meeting except that DMA/flush reply (which I have in a draft...)?
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<drewfustini> rory_be: I was reading the scroll back... the cores in rk3588 support big endian?
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<rory_be> Yes, the rk3588 supports big-endian
<rory_be> pabds3: Both emulation and hardware are a problem... Both VisionFive 2 and Star64 boards are ordered but still weeks out for delivery. I attempted QEMU, but big-endian support was left out so I moved to Spike, only to find it does not support linked libraries in pk mode.
<rory_be> Looking to try to patch QEMU...
<pabs3> rory_be: does the vf2/star64 hardware support BE??
* pabs3 thought RV was LE only :)
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<palmer> pabs3: BE was there, then it got removed, then it got re-added
<palmer> (pretty sure there's no BE hardware)
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<conchuod> drmpeg: rc3 looking good so far for me
<drewfustini> I think that OpenSBI and Linux support sparse hart IDs including not starting at 0. Anyone have experience with that working okay?
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<conchuod> Don't all the SiFive things work like that since hart 0 is the "monitor" core?
<jrtc27> not sparse, but yes
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<conchuod> We've used sparse & non-zero in Linux fine.
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<bjdooks> drewfustini: the unmatches just ignores hart0 under linux
<Tenkawa> I've noticed it seems to consistently register like this (at least on the mainline kernel)
<Tenkawa> [ 0.000000] riscv-timer: riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
<Tenkawa> on the VisioonFive2
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<courmisch> what's the exact -march for VF2? rv64gc_zba_zbb ?
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<Tenkawa> I'm seeing conflicting responses
<Tenkawa> my compiler is running -march=rv64imac -mabi=lp64 however Gentoo documents for example (which might be cross build) use -march=rv64gc -mabi=lp64d
<courmisch> your compiler just disabled the FPU...
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<Tenkawa> That's the Debian and vendor standard build settings
<Tenkawa> As far as I know I/we haven't done anything to override it
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<Tenkawa> That "might" be being set by the kernel sources though
<Tenkawa> I should check that
<Tenkawa> And since I'm testing with clang/llvm all bets are off
<drewfustini> Thanks bjdooks and conchuod
<conchuod> Tenkawa: Linux explicitly removes fd from march, I wouldn't use it as your basis
<Tenkawa> rebuilding with gcc now
<conchuod> KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
<conchuod> KBUILD_AFLAGS gets fd, CFLAGS does not.
<conchuod> Well, it does if you enable CONFIG_FPU
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<Tenkawa> indeed
<Tenkawa> CONFIG_FPU=y
<courmisch> well, but what extensions does VF2 support besides the obvious MAFD and C
<Tenkawa> From what I am reading.. not a lot
<Tenkawa> I'm looking at its documentation now
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<Tenkawa> Looks like these were the recommended
<Tenkawa> -mabi=lp64d -march=rv64imafdc_zicsr_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series
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<Tenkawa> going to rerun a build with those in my build explicitly now
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<courmisch> ziscr is unlikely to affect the compiler code generation, AFAIU
<courmisch> zba OTOH has dramatic effects on the byte code, though I don't know how much it actually does on perf
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<Tenkawa> It would apppear the zicsr extension causes: Error: unrecognized opcode `fence.i', extension `zifencei' required as well
<Tenkawa> running again with it pulled
<Tenkawa> It needs a newer compiler build
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<conchuod> It has zicsr_zifencei
<courmisch> is that used for anything other than custom asm? atomics?
<jrtc27> __builtin_cyclecounter()
<courmisch> to make rdcycle more accurate?
<jrtc27> if you don't have zicsr there's no CSR to read
<conchuod> Tenkawa: I suspect that whatever doc the starfive people have was produced between zicsr being created and zifencei being created
<Tenkawa> It can't be handled by the current gcc version..
<courmisch> jrtc27: I meant the fence
<Tenkawa> I found a bug report on it
<Tenkawa> My gcc is too old
<courmisch> I suppose that could be used by JITs, but I can't imagine GCC using it
<jrtc27> fence.i shouldn't even be used by userspace as the ISA is broken
<conchuod> s/fence.i shouldn't even be used by userspace as //
<Tenkawa> then again... I discovered Debian also isn't using hard float abi either
<jrtc27> idk, add seems fine :)
<Tenkawa> so I had to set everything to lp64 instead of lp64d
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<courmisch> gcc -dM -E - < /dev/null|grep abi
<courmisch> #define __riscv_float_abi_double 1
<courmisch> That's Debian unstable
<courmisch> looks like lp64d to me
<courmisch> which it should be. Disabling requiring D but then disabling hard float would be dumb
<Tenkawa> well there is a bug report out about it
<Tenkawa> looks older but it still gave me the error...
<Tenkawa> so *shrug*
<Tenkawa> Let me try something
<Tenkawa> its something with the linker...
<Tenkawa> courmisch: lol.... typo
<Tenkawa> thats what was causing the hard float error
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<rory_be> palmer: looks like you are correct. No BE hardware available so far... so I'm just going to stick with ARM for a while. Still waiting for an answer on horse creek though.
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<conchuod> rory_be: on whether horse creek will support bigendian?
<rory_be> yes
<conchuod> I dunno if bjdooks can actually tell you for certain, but I figure it's highly unlikely?
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<jrtc27> I'd put a lot of money on no
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<bjdooks> No idea
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<palmer> bjoto: one of those patches I queued is failing to boot for LLVM builds, I'm going to at least try and figure out which series it is. IIRC that had happened before...
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<nathanchance> palmer: Don’t hesitate to shout if it ends up being one of our bugs :)
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<palmer> nathanchance: it's looking like the command-line VA width patch is triggering the failures <https://lore.kernel.org/all/20230329050951.66085-2-alexghiti@rivosinc.com/>
<palmer> that's doing some makefile twiddling, so maybe we missed a clang-specific flag?
<nathanchance> Hmmm…
<nathanchance> That is certainly possible
<nathanchance> Or is there some flag that should not be there that is?
<palmer> yep, could be
<palmer> I'm just re-spinning everything to make sure it's actually that patch...
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<nathanchance> I am in the middle of another bisect; once I have that one sufficiently triaged, I can see if I can help get to the bottom of this. Something that is probably worth trying is ‘CC=clang CROSS_COMPILE=… LLVM_IAS=0’ instead of ‘LLVM=1’ to see if it is just a compiler problem, as opposed to assembler or linker (although it does not rule anything out for certain, just helps an initial focus)
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<palmer> I'm going to update to LLVM 16 first, I'm still on 15
<palmer> the update's worth doing anyway, if it fixes the problem at least we'll have something to run with
<nathanchance> Yeah good point, being able to bisect is a life saver
<palmer> yep
<palmer> it might take a bit to churn, IDK how fast this box builds LLVM...
<palmer> (I know Philip was complaining earlier this week about how our corp machines are really bad at LLVM builds for some reason)
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<jrtc27> just make sure you don't link with BFD, unless you like watching paint dry
<jrtc27> LLD and gold both run circles around it (LLD preferable if available; faster and actually maintained)
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<heat> beware that older LLD did not support riscv linker relaxation
<conchuod> Isn't gold "banned" in Linux for being shit?
<heat> yes, but we're talking about LLVM builds (llvm-project) I believe
<conchuod> Ah
<conchuod> heh, Atish & co busy tonight..
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<jrtc27> yeah this is just building an LLVM toolchain to build Linux
<jrtc27> and I doubt anyone's expecting that to go fast on RISC-V
<heat> also, check your LTO and your parallel link jobs
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<palmer> nathanchance: 16 is looking good so far
<palmer> (specifically 16.0.2)
<palmer> conchuod: you're talking about the CoVE stuff?
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<q66> heat: lto with clang/lld is still broken on riscv