sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<geertu> conchuod: Thx a lot for dlg,da9063.yaml! Now I just have to fix my subnodes names "wdt" ;-)
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<geertu> named
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<dramforever> <dramforever> i feel like wasm isn't really even supposed to be a stack machine
<dramforever> <dramforever> it's more like some sort of structured encoding of an SSA form to me
<dramforever> oof, accidentally pasted the wrong thing, please ignore
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<conordooley> geertu:)   yaml conversions are always a lot more work than I think theyre going to be
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<geertu> conchuod: I depends. Some are very simple. But these usually have been completed already ;-)
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<conchuod> geertu: I find it hard to grep for examples too & I don't really wanna bother people about my struggles with json-schema clauses
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<muurkha> is SeRV really RISC-V compliant even though it doesn't trap on illegal instructions?
<drewfustini> mmind00: looks like you are speaking about RISC-V Kernel at Embedded World. I'd love to see the slides if you are able to post a link sometime. Unfortunately I wasn't able to be there this year
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<geertu> drewfustini: I guess you're in Austin?
<drewfustini> Hi, no, at home in Oregon. I'm looking forward to Dublin though!
<drewfustini> Are you there? Bartosz should be too
<geertu> drewfustini: No, @home, too
<drewfustini> Ah ok. I just logged into the platform earlier to check it out
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<muurkha> interesting, LCSC lists the GD32VF103 as "discontinued"! Is there a replacement?
<muurkha> I wonder what happened — did ST sue them for using their register maps? it seems unlikely because they still have GD32F ARM parts: https://lcsc.com/products/Microcontroller-Units-MCUs-MPUs-SOCs_11329.html?keyword=GD32F10
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