klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
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<rwxr-xr-x> hey all!
<gamozo> Hai
<rwxr-xr-x> I've been following some tutorials on writing an OS, and really like the change of pace of writing in asm, so here come my insane idea, what if I never load a kernel and do literally everything in asm?
<rwxr-xr-x> it'll be a minimal os, that's for sure, but i want to know if it's feasable
<zid> your kernel is then written in assembly
<Mutabah> You can write a full kernel in asm
<zid> you can if you want, it's just ballache and not portable
<Mutabah> There was/is a large-ish project that has done exactly that
<rwxr-xr-x> oh shit i never even thought of that
<rwxr-xr-x> Oh and portability
<Mutabah> (MenuetOS iirc)
<rwxr-xr-x> let me check it out
<gamozo> I did that for some of my big kernels, mainly because I didn't want to faff about with compiler/libc stuff at the time
<gamozo> It's really not that awful for x86 since it's such a CISC ISA, terrible for other arches and portability
<rwxr-xr-x> that's one part of what I was thinking, c is giving me headaches
<rwxr-xr-x> cool
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<gamozo> Long term it's not great, but for dabblin it's a good way to go. And you're confident in how things lay out in memory and stuff
<gamozo> Idk, to me it was kinda nice
<gamozo> Once you get enough confidence in linking/compilers/wirting ELF/PE loaders, then it's probably worth switching to a language
<rwxr-xr-x> yeah, i started messing around because its a fun way to learn assembly, i didn't come here for low level C code, i already write that daily lol
<rwxr-xr-x> Sounds good
<rwxr-xr-x> Also, it is MenuetOS Mutabah
<rwxr-xr-x> Seems like the main selling point is speed
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<rwxr-xr-x> But they went beyond terminal, it has a desktop, which baffles me
<rwxr-xr-x> Thanks for the info! I'm gonna work on this!
<Mutabah> Speed is a strange reason... because beating an optimising compiler takes some considerable effort
<zid> yea speed is really really hard to achieve if you're hand writing
<zid> like, *really* hard
<geist> i think the main thing you can do if you're willing to mega cheat is pack it in a lot tighter
<rwxr-xr-x> "Menuet supports both 64 and 32bit x86 assembly programming for smaller, faster and less resource hungry applications."
<rwxr-xr-x> Interesting
<geist> specifically things like manually globally optimizing things, cheating on the calling convention, etc
<zid> I'm not beating LTO even if I try to
<geist> but even that is somewhat of a lost cause to modern LTO, right
<clever> rwxr-xr-x: part of what makes 64bit more expensive, is that all pointers are 64bits, double in size, so pointer heavy structures nearly double in size
<geist> good solid global optimizations are kinda the last real frontier of compilers kicking the shit out of humans
<clever> rwxr-xr-x: but there is a variant of the 64bit ABI, that only has 32bit pointers, solving that, while still having access to 64bit features
<gamozo> Def hard to beat compilers... although LLVM does some gross stuff and really is starting to annoy me
<geist> it's all fresh on my mind beacuse i've been piddling with apple2 asm the last few days and it's always fun to dig into the apple 2 rom to see how tight stuff is packed in
<rwxr-xr-x> Got it clever
<rwxr-xr-x> Thanks!
<gamozo> Grumble grumble https://rust.godbolt.org/z/vbT3zfcdn
<bslsk05> ​rust.godbolt.org: Compiler Explorer
<clever> rwxr-xr-x: but i dont see many people using that ABI
<gamozo> Can't merge the two 4-byte bounds checks into one 8...
<geist> gamozo: yeah clang in particular has weirder and weirder codegen the tighter you zoom in
<gamozo> Honestly, I think the problem is it's a playground for really complex optimizations, which then get in the way of the basic ones
<geist> i get the feeling that overall it's perfectly capable compiler, but it feels like a compiler written against benchmarks, not as a series of hand tuned optimizations
<gamozo> Things internally explode in state, and then some simple things end up becoming too complex to reason able. Or ordering matters in the passes, etc
<gamozo> yuuup
<geist> ie, kinda looks like something a machine learning system would make, but probably still is fast anyway
<geist> but really i think a lot of it is just pointing out that modern x86 machines at least can eat up garbage code and deal with it well
<gamozo> I playeed around with the GCC backend for Rust but no luck, all trait calls were function calls. Maybe I did something wrong? But I followed all the optimized/release instructions :shrug:
<gamozo> They really can lol
<gamozo> I wanna play around with the M1 (or M2 at this point?)
<geist> but i also dont like clangs codegen when you try to tune it for small codegen or something very clever for a particular algorithm. it tends to fail me more than gcc
<geist> it feels less 'stable' overall. small changes to input may cause it to generate wildly different code based on what path it took internally
<geist> OTOH its definitely getting sloely better. at least its perfectly capable system compiler, just strange output that runs well enough anyway
<gamozo> Yeah, I definitely perfer it for cross-arch stuff
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<veles2001> Clang goes a little overboard with the optimizations sometimes https://godbolt.org/z/PbaGbjerG
<bslsk05> ​godbolt.org: Compiler Explorer
<heat> nah, that makes total sense
<heat> it's trying to unroll your loop
<heat> why does it generate nasty asm? because you told it it can't use memcpy
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<veles2001> It's kinda impressive that it can unroll it to that extent
<mrvn> Does that unrolling actually help though? Aren't modern CPUs really optimized to running loops?
<mrvn> veles2001: try -Os with clang to get more reasonable code
<Mutabah> I was about to claim that a missing branch is better than a predicted branch...
<Mutabah> but a small loop in icache might be better than a massive one
<veles2001> That's what I'm thinking
<Mutabah> (iirc any CPU in the last 10 years should have `rep movsb` optimised)
<mrvn> And looking at the code it all is using r10/r11. Doesn't that cuase a register dependency or does register renaming take care of that?
<Mutabah> renaming should handle all of that
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<mrvn> Then what is actually the point of r11 in that code?
<heat> Mutabah, rep movsb is not that fast
<mrvn> or the order of offsets? 24, 16, 0+8 in parallel, 56, 48, 32+40, 88, 80, 62+72, ..
<mrvn> and sometimes it's read r10, read r11, write r11, write r10. and other times it's read r10, read r11, write r10, write r11
<mrvn> Wouldn't it be far better to do sequential memory access?
<kazinsal> erms seems optimized in the case of > 128 bytes && < 4096 bytes
<heat> glibc avx2 memcpy blows rep movsb out the water
<mrvn> heat: but this is -mno-sse
<heat> 1) mno-sse doesn't imply mno-avx 2) i'm talking about strictly rep movsb speed
<kazinsal> iirc it also suffers if it crosses a page boundary
<heat> in fact, if you re-enable builtins clang doesn't opt for memcpy there, so I was completely wrong
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<kazinsal> the CPU can only "buffer" enhanced rep movsb until it hits a page boundary, then it has to stop and re set-up the whole thing
<kazinsal> and erms has a spool-up time
<mrvn> kazinsal: doesn't that get pipelined?
<heat> i've never read that before
<kazinsal> I'm not sure, in my testing every time you get to the point of "lol new page" the whole thing goes "faaaaaart" and starts over
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<kazinsal> it's something like 35-40 cycles to start up an erms
<mrvn> does "rep movsb" do a single TLB lookup and then run till the end of the page? Does that mean for 2MB pages it runs for 2MB before reset?
<kazinsal> not sure, haven't tried with large pages
<heat> i'm not sure that holds up with my measurements
<mrvn> would make sense though if it eliminated the TLB loookup for sequential access
* heat looks for the bench results
<kazinsal> it's also entirely possible that, knowing intel, the nitty-gritty of this changes every time they microwave a core, feed it more amps, and increment a digit in the model number
<bslsk05> ​gist.github.com: gist:0d107a2933f81e81cc649dd6bf06962e · GitHub
<heat> this is erms memcpy vs glibc memcpy on a 2018 kabylake r
<bslsk05> ​gist.github.com: bionic_bench.cpp · GitHub
<heat> in my experience erms performs mostly around SSE2 levels
<mrvn> What I don't get is how "rep movsb" gets optimized into something slower than sse/avx. Shouldn't the CPU see that the count is larger than a cacheline and then issue cacheline fetch/store? or whatever avx does as largest.
<heat> also funnily enough rep movsq is as fast as rep movsb in my hw
<mrvn> heat: so at least it detects if the count is >= 2, 4, 8
<heat> hm?
<kazinsal> part of me wonders if erms is specifically an "increase apparent IPC by speeding up shitty old code" feature
<heat> it does not
<mrvn> heat: if it's the same speed then it's combining the read and write
<heat> no, it's that in the rep movs<size>, the <size> doesn't really matter, it just helps determine the total length
<mrvn> or the limiting factor is your memory and it doesn't matter how the cpu access it.
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<heat> kazinsal, intel throws a crazy amount of effort optimizing glibc functions for the latest and greatest SIMD
<heat> you even have avx512 stringops now
<mrvn> "rep movs<size>" should just program a DMA engine in the CPU and be the fastest way
<kazinsal> oh yeah but "let's make rep movsb faster" feels really weird when they've simultaneously been doing that
<heat> I assume rep movsb is a best effort at a one size fits all memcpy instruction
<kazinsal> it feels entirely like "those dorks at phoronix are still running a benchmark that does rep movsb, let's make the numbers weird"
<heat> noooooo not phoronix
<heat> fwiw linux did really naive memcpies to usermode using rep movsb until a few months ago
<mrvn> heat: I can see how that would increase the cost to set up but if your count is large it should issue the largest read and write instructions the bus has and nothing else should be faster.
<heat> listen, I don't know, I don't design CPUs. there has to be a practical reason as to why that's not possible
<mrvn> only intel/amd could explain that and probably nobody can due to NDA.
<heat> or arm or sifive or... ;)
<AmyMalik> we need to endthe era of the CPU
<mrvn> As a programmer those quirks just make no sense.
<heat> this isn't paticularly top secret
<mrvn> heat: arm has no "rep". Does any modern cpu have it?
<mrvn> Most I've seen on other cpus is a "decrement and branch" opcode.
<kazinsal> someone will propose an extension to risc-v eventually
<heat> arm doesn't have rep but they AFAIK have a sanctioned "this is the best way to copy memory"
<AmyMalik> the lisp will rise again
<mrvn> ARM also has a much harder time with unaligned copying.
<heat> arm64?
<mrvn> Does ARM64 still have the trap on unaligned control bit?
<heat> probably
<veles2001> Yup
<AmyMalik> kazinsal, microwave, amps, digit?
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<AmyMalik> eggs plane?
<mrvn> Lebkjuchen
<heat> how do I effectively relax a jmp?
<heat> like jmp imm32 -> jmp imm8
<heat> memcpy every opcode I issued back? then reprocess relocations?
<heat> I could just nop the rest out but that seems non-optimal
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<bslsk05> ​eli.thegreenplace.net: Assembler relaxation - Eli Bendersky's website
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<moon-child> heat: you need an smt solver
<heat> for what and why
<moon-child> your assembler thingy
<moon-child> in the general case, it's an annoying nonlocal problem
<moon-child> otherwise you can just do a fixed-size window where you overestimate instruction sizes and just use the small form if it'll definitely fit
<moon-child> that'll give you 99%
<heat> ok, lets start from the beginning: what's an SMT solver and why does my thing not work
<heat> (my thing = my idea)
<heat> given that LLVM already does my idea
<moon-child> what's your idea?
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<heat> go through every jmp and see if we can relax imm32 into imm8; if so, do it, move opcodes around and recalculate every jmp
<heat> keep doing it until things stop moving
<moon-child> you can have circular dependencies. So jump X is small only if jump Y is, but jump Y is small only if jump X is
<heat> so none of them get a small jmp
<heat> oh well!
<heat> I don't expect to lose much from that corner case
<moon-child> then don't bother with 'waiting until things stabilise'. Just use a fixed window
<heat> meh
<heat> I think I'll skip this problem for now
<heat> just to be clear, this is not an assembler but a jitter
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<heat> so I pretty much don't need to take care of that problem if its that painstaking. i can take care of it by not taking care of it, or using my naive-ish solution
<heat> in any case I'm relatively happy as it's miles faster than interpreting
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<moon-child> what is it for?
<heat> bpf
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<heat> hmm maybe going for a short jmp thing would be a good idea
<heat> I could save 8 bytes of instructions on this bpf program
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<mrvn> moon-child: but why can't you go at it from the other side? Make everything an imm8 jump. Then change those that don't work to imm16 and recalculate till all fit.
<bslsk05> ​gist.github.com: gist:4cc7912027caea63df8a96e73b185aca · GitHub
<heat> this looks weird on the ret but I'm relatively proud
<heat> there's not much I can do here to shorten things unless I actively try to merge instructions
<heat> and do more complex transformations
<mrvn> moon-child: I can't see any way that enlarging a jump would make another suddenly shrink so you can't have the x/y dependencies that way
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<heat> if I give gcc a C description for this program it can generate something wayyy tidier
<heat> which is, erm, unfair
<mrvn> heat: do you have a red-zone? Do you need a frame pointer for debug or something?
<heat> I want it for debug yeah
<heat> but that would save me very few instructions anyway
<mrvn> you can zero %eax and use a cmov for line 18
<mrvn> saves you 3 opcodes
<heat> <heat> there's not much I can do here to shorten things unless I actively try to merge instructions
<heat> <heat> and do more complex transformations
<mrvn> what generates the BPF struct?
<heat> <load eax> + pop rbp + ret is a straight up jit of BPF_RET
<heat> in the case of classic bpf, an assembler or a manual program
<heat> or something hardcoded by a human ofc
<mrvn> So you just have blocks of asm for each BPF_STMT and plug that in?
<heat> eBPF can be generated by the above plus a compiler like clang
<heat> can you rephrase that?
<heat> I have a bunch of opcodes sequences and routines that output those sequences, frequently looking at compile-time data like constants
<heat> i.e add $1, %eax -> inc %eax
<mrvn> "<load eax> + pop rbp + ret is a straight up jit of BPF_RE" That sounds like you have a simple mapping from BPF_STMT to blocks of asm.
<heat> well, yes, each bpf statement maps to some possible instructions, there's no peephole here
<heat> but it's not as dumb as a BPF_STMT -> u8[]
<mrvn> obviously. you have to include the parameters
<mrvn> heat: so how about starting your code of with generating short jumps and then growing jumps as needed?
<heat> that works as long as I disallow backwards jmps I think
<mrvn> .oO(Can you have BPF_JUMP(..., 4, 5)?)
<mrvn> heat: shouldn't be a problem. You check all jumps, if any needs to grow you repeat. At some point that settles.
<heat> wdym BPF_JUMP 4,5?
<mrvn> For large code you would want to limit the jumps you have to check again after each change but that's an optimization that doesn't change the result.
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<mrvn> heat: You jump's are all "continue if true, jump ahead otherwise" Does one of the offsets always have to be 0?
<heat> no
<mrvn> So between lines 14/15 you had a "jeq 0x15" that got eliminated?
<heat> yup
<mrvn> Does that also work if the offstes are swapped: ", 3, 0)"?
<heat> yes
<mrvn> I bet jumps where one branch isn't "0" are rare.
<heat> /shrug
<mrvn> the xchg + cmp could be otimized to byte swap the constant
<heat> yes, gcc does that
<heat> again, no peephole here
<heat> I'm basically relying a good bit on the bpf writer having an IQ above 10
<mrvn> Is the xchg from the BPF_LD statement?
<heat> yep
<heat> the xchg is a byteswap for packet data since cBPF tells you to swap packet data
<heat> this will ultimately be conditional on if the bpf program is getting applied to networking stuff or other things that don't need bswap (like seccomp)
<moon-child> mrvn: if all you have is jumps, then you can do that, yes. But if you also have alignment directives, then you can create a situation where making one part of the code bigger makes another part smaller
<bslsk05> ​github.com: bpf-interpreter/x86jit.cpp at main · heatd/bpf-interpreter · GitHub
<heat> my 80% ready jitter
<kazinsal> fairly simple jits are always a fun exercise
<heat> this did not feel simple
<heat> 1) it was my first jitter; 2) x86 3) x86 4) needs to be secure since it will be at a privilege boundary
<kazinsal> 5) c++ templates
<heat> i'm not using templates
<heat> do you think i'm a hippie or what
<mrvn> moon-child: because some code will not move and if a jump crosses padding then it can shrink. ok.
<moon-child> 'std::vector<u8> data_' idk man, looks a lot like a template to me
<mrvn> moon-child: but then you have a case that simply can't be resolved. If jmp x is small then jmp y must be big and vice versa.
<moon-child> indeed. You have to pick one. Can try to minimise global size or something
<mrvn> moon-child: that quickly goes into exponential time.
<heat> that's not a template
<heat> it's a lesser than u8 greater than
<moon-child> fwiw it's also nice to be able to construct arbitrary expressions using labels and have it be optimised properly. https://redd.it/y8pn5z one problem I ran into, that I wouldn't have had if my assembler had come with an smt solver
<bslsk05> ​redirect -> www.reddit.com: Alignment : asm
<moon-child> heat: ah! My mistake
<heat> ebpf even has atomics huh
<moon-child> 'The fact that [redox os] is only getting around $1,000 per month on Patreon points to deep, deep flaws in humanity. Especially when you compare it to other funding amounts for say Linux or popular smut on Patreon. A total lack of foresight and values.'
<zid> $1000/mo is amazing
<zid> I wonder how much he thinks simon tatham makes from patreon
<heat> lmao
<moon-child> I mean
<moon-child> if I had any artistic skills I would totally do furry smut or w/e for coins
<zid> I knew it
<zid> I should have known from your hippie ass name
<kazinsal> lemme guess, that quote's from hackernews
<heat> no its from ma
<mrvn> $1000 is more than I had to live of as student
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<gog> meow
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* kazinsal pets gog
* gog prr
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<FireFly> :3
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<vdamewood> Oh... kitty go bye bye.
* vdamewood looks sadly at his fishy.
<FireFly> meow
* vdamewood checks his bag. Finds extra fishies.
* vdamewood gives FireFly a fishy.
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<FireFly> nom
* vdamewood gives gog a fishy
* gog chomp
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* moon-child rubs against vdamewood's legs
* vdamewood gives moon-child a fishy
<sham1> Aaa, too bored
<GeDaMo> 2bored4osdev? :|
* rein-er boots Minix
<zid> imagine having the energy to osdev
* vdamewood has flashbacks of Pokémon.
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<sham1> GeDaMo: too bored at work. Nothing's working and everything sucks
<GeDaMo> That's just life :|
<rein-er> imagine having to debug the serial driver using nothing but a scope on an unsupported and undocumented platform 😭
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<vdamewood> rein-er: That sounds like fun, actually.
<vdamewood> rein-er: Well, maybe, what kind of 'platform'?
<bslsk05> ​'Quake on an oscilloscope' by pekkavaa (00:03:27)
<vdamewood> GeDaMo: I wonder what the audio that generated that sounds like.
<bslsk05> ​www.lofibucket.com: Quake on an oscilloscope: A technical report
<GeDaMo> Meh, I don't know if I could dance to it :P
<rein-er> vdamewood it is fun but.. well the problem is that its hard to know which one I have https://web.archive.org/web/20110902100901/http://wiki.s1mp3.org/S1mp3_device_database
<bslsk05> ​web.archive.org: S1MP3 Wiki - S1mp3 device database
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<vdamewood> GeDaMo: I think this signal is ruining my speakers
<GeDaMo> Maybe you should turn it off then :|
<zid> It's making them.. quake
* zid leaves
<vdamewood> Oh, I have moe cards to sort out!
<vdamewood> Oh, wrong channel for that comment.
<zid> I only have tsudere cards :(
<zid> tsundere*
<vdamewood> Mine are Crack: The Gathering
<zid> I don't have enough solid gold ferraris to play CtG
<vdamewood> You only need one
<zid> Yea well I have 0, w hich is not enough
* vdamewood gives zid a solid-gold Farrari
<zid> haha you fool, I'm selling it to buy pokémon cards
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<vdamewood> I'll get my Pokémon deck.
<zid> Deck? pfft. I just want every single copy of fat pikachu.
<heat> hey friendos
<heat> help
<heat> 89 44 24 04 mov %eax,0x4(%rsp)
<heat> what's the "24" here?
<heat> is this a SIB byte? modRM?
<heat> It has been two days and I still understand jackshit of what the intel SDM says
<GeDaMo> Doesn't zid have a website which explains machine code?
<zid> not yet
<zid> [--][--]
<kazinsal> I think 24 is the SIB
<kazinsal> iirc it's { prefix opcode modr/m sib disp imm }
<GeDaMo> zid: is this not yours? https://dis.yaxpeax.net/x86:32/89442404
<bslsk05> ​dis.yaxpeax.net <no title>
<zid> nope
<zid> that's a cool link though
<kazinsal> ooh, I am definitely bookmarking that
<zid> I never remember about it, seen it a couple of times now
<GeDaMo> I'm sure I got it from ##asm
<zid> It could do with writing some hex across the top
<zid> not just the binary
<heat> ohh
<kazinsal> yeah
<heat> so rsp needs the SIB
<kazinsal> but that's handy
<kazinsal> much better than trying to look up stuff in the SDM
<zid> That's why I keep saying we should replace the hardcoded rax stuff with hardcoded rsp stuff :P
<zid> it's more useful 90% of the time
<heat> why does only rsp need the SIB?
<kazinsal> too many registers
<heat> or at least some registers clearly don't need the sib
<zid> everybody used to use ebp
<kazinsal> the 100 in the r/m field specifies a SIB byte follows
<GeDaMo> in 16 bit mode, only certain combinations were valid
<zid> yea, 4/c/14/1c/24/2c/34/3c row == 100 r/m
<GeDaMo> You also need SIB if you want a multipler
<kazinsal> if mod is 11 though then r/m 100 means esp with no displacement, no SIB
<zid> [ebp]+disp8 exists, which was fine.. when we used stack frames
<kazinsal> complex instruction set computing!
<heat> mov %eax,0xc(%rbp,%riz,1)
<heat> look, a ghost register!
<zid> that's just AT&T being fuckshit
<heat> rizzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz best register
<zid> can't parse it if there's no register name in there that it understands
<GeDaMo> That site works for other architectures https://dis.yaxpeax.net/
<bslsk05> ​dis.yaxpeax.net <no title>
<j`ey> > Internal Server Error
<kazinsal> boo, no z80
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<zid> oh, everybody go home then, terrible website
<heat> erm
<heat> mov %eax, (%rbp) -> why does this always get a 0 offset in the opcode
<heat> what's wrong with this wretched instruction set
<Mutabah> because there's no offset?
<heat> well, no, other registers have short forms
<heat> mov %eax,(%rdx) -> 89 02
<heat> mov %eax, (%rbp) -> 89 45 00
<Mutabah> aaah
<Mutabah> Just looked up some old notes: The slot taht would be `BP+0` is used for imm16
<Mutabah> This is because 99% of the time, BP is used relative
<heat> .....................................
<heat> fml
<bslsk05> ​github.com: rme2/rme.c at master · thepowersgang/rme2 · GitHub
<kazinsal> modr/m is pretty funky
<Mutabah> The same rule applies to the 32-bit version (BP with no offset is actually an immediate address)
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* Mutabah reads DoFunc32 and scratches head
<Mutabah> is that segment register logic correct?
<kazinsal> I... don't think so
<kazinsal> off the top of my head that register order doesn't make sense for default Sreg
<kazinsal> but I'm also a bit out of it
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<Mutabah> kazinsal: Yeah, that doesn't make sense - it was a copy-paste from the 16-bit code
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<kaichiuchi> please tell me how to get the duck song out of my head
<kaichiuchi> someone
<kaichiuchi> anyone
<kof123> i dont know what that is, but fire with fire, must replace it with something equally annoying
<kaichiuchi> it's best that you do not know
<kaichiuchi> it will become stuck in your head and it will haunt your dreams.
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<mjg> kaichiuchi: search for 'schnappi das kleine krokodil'
<mjg> you are welcome
<kaichiuchi> not bad.
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<sham1> mjg: damn you, now you've gotten that song into *my* head
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<sbalmos> too early on a Monday to be doing these mental gymnastics, but here goes anyway... I'm paper-designing my VFS, and at the moment I want to enforce strict separation between a partition/volume that has installed apps, which is the only place the system can run programs from and is marked executable+user-RO, vs a data partition/volume that is marked non-executable+user-RW. I'm trying to think through
<sbalmos> supporting dev on this type of layout... maybe taking a page from Fuchsia and requiring a temporary packaging after build that is system-"installed" to the app volume?
<sbalmos> But then I think about interpreted/script-type languages like Python, where executable libs are not really discernable from free-text "user data" that would be on the data volume
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<kof123> hmm...i would wager a typical unix executable bit serves a dual purpose, binary or script "executables". thus, if they should be separated, add another bit to distinguish? and/or another "script" partition? whether that meshes with existing stuff...also, a way to make that mesh may be: what about symlinks to another partition? hmm....
<kof123> not saying allowing such symlinks is a good idea, just pointing out a decision needs made there perhaps
<kof123> i am not a good example, i would just add a bit in the name of flexibility
<kof123> and sort out the details later
<GeDaMo> Isn't an executable bit a specialized version of "what do I do with this file type?"
<GeDaMo> Hmmm ... I suppose you might want to disable certain executable files
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<kof123> well...not saying adding a bit is a good idea....just if they should be separate, make it so
<kof123> i also don't care about back compat per se, so that is the downside if one does: would then have to package things accordingly
<sbalmos> playing off that idea for a moment, maybe not so much an executable bit, but a manual way of granting execution/system-mod privileges to a directory tree
<kof123> yeah lol
<kof123> lol because my fs ideas i have bunch of stuff "fs-wide" ...but also toying with directory wide/recursive. i sometimes want both, but the latter, set on the "root" directory (or mount point) would suffice for some stuff
<sbalmos> like system-wide Python libs etc would already be installed into the app volume anyway. but for user Python libs, etc, maybe a form of the old bless command that says "I grant this directory tree these app-like privs..."
<sbalmos> (not just execute, but more granular)
<kof123> bless command?
<GeDaMo> Don't Windows directories inherit properties from their parent?
<sbalmos> ACLs
<sbalmos> not necessarily "properties"
<GeDaMo> Ah
<sbalmos> and what I'm thinking is more than just "give everything in this tree the ability to be executed". It's also like "give everything in this tree execute, give only scripts in this subdirectory in there network access, give this other subdirectory access to these certain other users' data volumes (but still nothing touches system volume)", etc
<sbalmos> also goes along that my VFS is not strictly tree-like. it's more tag/attribute/persistent-search based. filenames and containing directories are optional.
<kof123> makes sense
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<sbalmos> huh, that actually gave me a follow-on idea. so to me, at least on the paper VFS, a directory is just another object type that can contain others. So technically I could have an object type of "Python project" or such, which the system has already predefined as having certain rights like "objects of type blah contained in this object can be executed using app blah on the app volume (e.g. the python
<sbalmos> interpreter)" along with rights to access the system-wide Python libs in the app volume. You'd create a new "Python project" object in your user data volume, add other objects (nominally of text-type or text-like, doesn't really matter), boom.
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<mrvn> isn't that what SELiux does?
<sbalmos> in concept. but it's still bolt-on, and how many times have you seen SELinux just disabled because it doesn't have pervasive FS and GUI support etc?
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<netbsduser`> follow the object capability model and we will get some meaningful security
<sbalmos> at a single-sentence level... "yes"
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* geist yawns
<geist> good morning
<clever> evening
<sbalmos> g'day-quickly-turning-to-evening
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<sbalmos> I've gone down such a rathole today on selinux, fiddling with the half-crumpled bullet list of features/reqs/notes in my on-paper VFS design, etc.
<geist> tried to fix the old apple 2 power supply last night, shorted out something, popped a breaker, now it's more broken than before
<geist> but not is all lost! i have a replacement modern one anyway
<sbalmos> geist: you've seen the guy who slapped a RaspPi emulator into the apple 2 case?
<geist> yah. actually wha ti'm interested in now is a MISTR
<geist> there's a new all in one mistr retro kit board thing that looks fantastic
<geist> looks kinda like the linux of old hardware simulation, it beats everything else by if nothing else just havng all the mindshare
<bslsk05> ​savemyserver.com: Black Friday Servers | Black Friday Dell Deal | SaveMyServer
<geist> oh noice
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<heat> HELLO
<heat> i am back from the football
<heat> what did I miss
<geist> were you a hooligan?
<zid> heat: Three firebombs and 14 rocks, knowing your aim
<heat> no i couldn't get to qatar and back that quickly
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<sbalmos> so you went to your TV to watch, and now you're back?
<heat> no, i went out and met other people whom I consider friends, and watched it, and now I'm back
<sbalmos> geist: I honestly forget if we discussed this hypothetical at one point, but if all user services were restartable, and there was a way to pass a phymem address in a special "known location" at the kernel level, wouldn't it be possible to rolling hot-restart all CPUs on a new version of the kernel without a full reboot?
<sbalmos> heat: fr... friends? what's "friends", precious?
<heat> tv show from the 90s
<heat> geist, are you the CEO of x86? why are the opcodes so braindead
<geist> so insensitive!
<geist> the opcodes are a manifestation of my brain
<geist> i'm sorry i'm not perfect!
* geist runs out of the room crying
<sbalmos> Sensitivity fault: Core dumped
<heat> why does your brain have special cases for everything
<sbalmos> the previous attempts to stick a hot poker through the skull did not succeed
<sbalmos> it left scars
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* c2a1 sells all his gheist shares
<c2a1> *x86
<heat> noooooo not the poltergeist
<c2a1> why is there an ARM but no LEG
<zid> I mean, I'm sure you know the actual reason
<zid> x86 evolved organically and its motto is "fuck the decoder's complexity"
<c2a1> x86 is superior. eof
<heat> amd64 was supposed to be a clean break
<heat> where is it?
<c2a1> in amd's hands
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<jbowen> I do have legbsd.org registered
<heat> another bsd? what can go wrong
<jbowen> lol, no
<heat> but the BSD codebase is so high quality :(((
<heat> what's the matter of forking it, and this time for good
<jbowen> There was an armbsd.org that pointed at NetBSD images for ARM boards
<heat> I'll buy netbsd.com and point it at kernel.org
<jbowen> Someone made the ARM/LEG joke and I grabbed the domain
<zid> heat you're on top of reddit
<zid> #1 post atm
<heat> told ya
<heat> save ukraine and shoutout to my lgbtqi+ people
<mjg>  wut?
<mjg> that a joke or some sort
<mjg> someone else named heat?
<heat> zid does not joke around
<jbowen> слава
<mjg> 's going on dawg
<heat> neither do I
<heat> we're all very serious people
<mjg> cyka blyat jbowen
<heat> I'm writing this from a qatari jail
<zid> 'A man invades the pitch at the World Cup in Qatar with a shirt reading "Save Ukraine" and a rainbow flag during Portugal vs Uruguay' for mjg's reference I guess
<mjg> ok, that sounds like heat
<mjg> you go man
<mjg> boy boss
<heat> this is my next pitch invading shirt
<heat> sortie, sortix shirt when?????????
<sortie> u want ur sortix shit?!?z
<mjg> zid: heh
<sortie> go 2 the merch stand
<heat> wear
<heat> ?
<mjg> i heard people in pl referring to the spinning rust disk activity as "thinking by the computer"
<mjg> sortie: i'm in the market for 'sortix > onyx' shirts
<mjg> sortie: there is a dude i want to send one to
* sortie still has a mechanical harddrive like root intended
<heat> I'm in the market for shirts that say "Matthew Guzik = Mateusz Garret"
<sortie> I'd develop onyx on sortix but someone had the foresight to use cursed compiler tech
<mjg> heat: i'm waring one right now
<sortie> heat, you and me both
<sortie> heat, I did once explore Sortix mugs
<sortie> Should've made some
<heat> with cursed compiler tech do you mean a gcc newer than gcc 5
<sortie> heat, I mean clang
<heat> I do not require clang
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<sortie> I though you used clang?
<heat> even though I wholeheartedly stan clang and LLVM the best liberally licensed compiler
<heat> I use both
<sortie> onux works with gcc?
<sortie> onyx
<heat> yes ofc
<sortie> ...
<sortie> stand by
<sortie> gotta try ur hobby os
<heat> do you think this is amateur osdev where I only support a single compiler?
<mjg> or a single core?
* sortie takes one damage to hit points
<kaichiuchi> hi
<sortie> hiya kaichiuchi
<mjg> take your bullshit to #openbsd
<kaichiuchi> sortie: i've seen you before. where have I seen you before?
<heat> we should disable the other cores for security reasons
<zid> It's actually kinda nice if a PC makes different noises while it does stuff
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<sortie> kaichiuchi, I'm at lots of concerts
<zid> loading a game, keyboard no longer works, but the hdd is making noises? No panic.
<kaichiuchi> ah
<zid> Loading a game, keyboard no longer works, hdd is silent? panic.
<heat> yeah I've made my SSD play circus music on disk access
<heat> really calms my nerves sometimes
<sortie> https://pub.sortix.org/sortix/screenshots/sortix-cross-compiling-linux-kernel.png ← I once tried this Linux hobby OS I heard so much about but it paniced on boot
<sortie> Probably needs an initrd or root filesystem or something, maybe there's a guide on those to build those
<heat> -append noapic
<heat> what's wrong with the APIC
<c2a1> nice honeypot
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<heat> wizards of the deep
<heat> why does ppc context swap (ucontext) need a syscall? https://elixir.bootlin.com/linux/latest/source/arch/powerpc/kernel/signal_32.c#L917
<bslsk05> ​elixir.bootlin.com: signal_32.c - arch/powerpc/kernel/signal_32.c - Linux source code (v6.0.10) - Bootlin
<bslsk05> ​github.com: libucontext/swapcontext.S at master · kaniini/libucontext · GitHub
<c2a1> who even knows how to answer that if its ppc
<heat> geist probably
<heat> you severely underestimate the wizards of the deep
<zid> I need to come for 6 days 22 hours, how do?
<zid> coma*
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<heat> coming for 6 days and 22 hours is hard, most people can only do it for a few seconds
<zid> Just be a pig
<gog> geist is the architecture understander
<zid> gog the stripey socks understander?
<kaichiuchi> geist is the origin of all computing and we just don't know it
<gog> yes
<zid> I am currently attempting to understand the 23 honzuki novels, currently airing: volume 22
<zid> we're so close to me being done and just ending it all in a sea of fanta
<kazinsal> programming socks are important for ensuring your code compiles the first try
<FireFly> I learned recently there's a whole system in place
<bslsk05> ​Note by Chris Evelyn: "@sashag They even come in ranks. Here‘s a helpful chart:" https://assets.tech.lgbt/media_attachments/files/109/382/993/537/726/242/original/5b30a1be99b1624f.jpeg [Overknee stockings in trans colors, getting progressively more ornate, labeled „Junior“, „Senior“, „Team Lead“.]
<zid> yes, it's called the third impact
<zid> oh, socks, not fantas
<gog> true story, i wore stripey socks with cat faces on the knees to work today
<zid> gog: I'd go girl for those cute hoodies with cat ears, so I'm like 1/100 on the egg scale
<FireFly> ah you must be highranking
<gog> nah i'm a junoir dev
<zid> high archmage sock wearer though
<gog> tried to get my boss to wear them but he's not into it
<gog> yet
<zid> how egg scale is boss
<gog> -100
<zid> wow, that's way below me
<zid> I'm more girl than I thought
<FireFly> I'm still convinced these red-black striped ones are specifically tuned for implementing balanced binary trees
<gog> i need a pair of those
<FireFly> zid: you're allowed to wear cute things regardless of gender fwiw, y'know :p
<zid> nah I need to broadcast my masculinity, I have very little of it
<zid> I need to ration it
<zid> and not dilute it
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<kazinsal> fuck that, shave your legs and get a buttplug and become a better programmer
<gog> don't forget the coffee
<zid> I wouldn't mind shaving my legs
<zid> I basically can't wear socks
<kazinsal> day 1: smoooooth
<zid> my ankles end up totally on fire
<kazinsal> day 2: still smoooth
<kazinsal> day 3: ITCHY
<zid> And by shave I mean use a car battery
<zid> like a MAN
<FireFly> that's uh
<FireFly> some hardcore electrolysis
<gog> i need some of that
<gog> face by exide
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<FireFly> I don't think I've heard anyone try that approach, not sure it's recommended..
<kazinsal> the smooth is great but the itchy is hell
<zid> jacob's ladder and a car battery, what could go wrong
<gog> yeah i gotta find a professional i think
<zid> clever just has that link in his back pocket
<FireFly> clever: this causes pain just to look at
<clever> zid: i just happened to be posting it elsewhere a few minutes ago :P
<zid> sure sure :D
<zid> The last link I psoted is
<gog> this is like the third channel where i've had a conversation somehow go to inadvisable insertions
<gog> i didn't even start it
<FireFly> inadvisable insertion: at the end of a full array, requriring a reallocation
* FireFly nods
<zid> (greek friend)
<kazinsal> ensure your reallocation has a sufficiently flared base