klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
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<Imk0tter> is it more expensive to compute 2 / infinity than it is to compute 1 / infinity?
<zid> no? it's not computed at all
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<Imk0tter> if it is possible in the domain of mathematics, it it possible in the realm of computing?
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<geist> the proper response is to sit there starting off into the distance and then have your ears start to smoke and your head explode
<moon-child> Imk0tter: yes, but only in the round-to-nearest mode
<moon-child> because you get a quotient of 0 but a remainder of 2 vs 1. And you have to check that the remainder does not exceed infinity/2; this takes longer the closer the two comparands are
<moon-child> ;)
<moon-child> FUN FACT: infinity/infinity is actually 0.5. The reason for this is that, if you do integer division, you will get a quotient of 0 and a remainder of infinity. And infinity is the same as infinity/2
<moon-child> I'll be here all night, folks
<nur> lol
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<AmyMalik> moon-child: isn't it every real number at once?
<moon-child> yep. We can therefore conclude that 0.5 is also every real number at once
<zid> also 7
<zid> every number is 7
<zid> = is the seven operator, == is the "is seven" operator, etc
<moon-child> indeed
<moon-child> a surprising result of this is that 7/infinity is actually a complex number
<AmyMalik> consider building a tcl chip
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<Clockface> are there any kernel-mode only OS's besides templeOS
<Clockface> preferably not ancient history
<moon-child> singularity et al
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<geist> you can kinda argue that LittleKernel is, though depends on what you mean
<geist> also most embedded rtoses are effectively kernel only
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<kazinsal> there have been a few but they've generally been functionally unusable
<kazinsal> there is very little purpose in an operating system that you can pwn by sneezing at it
<moon-child> unlike privilege-separated oses, which ... you can also pwn by sneezing at
<moon-child> you _can_ do protection in software. Using sasos with such a design means that you can have very cheap, very expressive ipc
<moon-child> which encourages people to separate components of their applications into distinct trust domains. How many people actually do this under unix? Basically zero, because it's clunky and slow as all hell
<moon-child> I would therefore expect an sasos to lead to generally _more_ secure software
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* AmyMalik squeaks in qmail
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<rwxr-xr-x> Hey all, i've got a register i'm trying to mov into, and it isn't working. I use *in al, dx* and then try to mov al into bx, but it doesn't work. No idea why
<rwxr-xr-x> NASM says invalid combination of opcode and operands
<mrvn> intel vs. gnu?
<rwxr-xr-x> intel
<mrvn> You can't move 8 bit into 16 bit.
<rwxr-xr-x> So i need to use al or ah
<GeDaMo> movzx or movsx
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<rwxr-xr-x> let me look at those
<mrvn> I would have said you need to use ax.
<rwxr-xr-x> move with zero extend and move with sign extension, never heard of them
<mrvn> "try to mov al"
<rwxr-xr-x> Ohhh those are cool
<rwxr-xr-x> let me try that mvrn
<mrvn> You probably want to extend the 8bit so use what GeDaMo said
<mrvn> or just write an inline asm fuinction for "inb" and do everything in C and let the compiler figure it out
<rwxr-xr-x> yeah those instructions are really cool
<bslsk05> ​hbfs.wordpress.com: Branchless Equivalents of Simple Functions | Harder, Better, Faster, Stronger
<rwxr-xr-x> currently i'm writing everything in assembly, so inlining in c won't work
<GeDaMo> You can use sign extend to do branchless stuff
<mrvn> GeDaMo: your url assumes two's complement. It's implementation defined before c++23
<GeDaMo> Just write in asm! :P e.g. cwd; sub ax, dx; xor ax, dx; gets the absolute value of ax
<mrvn> GeDaMo: and is even more hardware specific
<mrvn> Also is that code better than "sub; cmov"?
<mrvn> or neg;cmov rather
<GeDaMo> I think it may vary depending on microarchitecture
<bslsk05> ​godbolt.org: Compiler Explorer
<mrvn> The whole article starts with the misconception that abs(x) uses a branch.
<mrvn> It's a good example to talk about branchless function but the compiler is already smart enough for it on it's own.
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<GeDaMo> Ah yes, sufficiently smart compiler :P
<bslsk05> ​'Can C++ be 10x Simpler & Safer? - Herb Sutter - CppCon 2022' by CppCon (01:53:59)
<sbalmos> screw it all, I'm switching to Zig
<mrvn> "Entropy will get us all in the end".
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* jbowen drinks to that
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<heat_> mrvn, from the little I've watched I'm already turned off by the horrid syntax
<heat_> like is this haskell or C++?
<heat_> I'm also consistently flabbergasted by the "modern C++ people"'s insistence on auto f(int n) -> int instead of int f(int n)
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<gorgonical> geist: how hard was it to get LK running in arm trustzone?
<gorgonical> or were you not involved with trusted lk?
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<clever> gorgonical: ive talked to him before about theories i had on porting it there, and the main issue is that a lot of the control regs are hard-coded with an EL1_ prefix (or was it a suffix?)
<gorgonical> probably the EL1_ prefix
<clever> gorgonical: ideally, you would make the primary EL a compile-time flag, so LK can run in EL3 or EL2 as well
<gorgonical> yeah. this problem was so big arm came up with vhe to get around it
<clever> and then #ifdef around a few differences, like EL2/EL3 not having 2 TTBR's
<clever> but VHE is only for making EL2 act like EL1?
<clever> and adding a second TTBR
<gorgonical> Oh right
<gorgonical> I guess a "similar" problem but not really the same
<clever> but EL3 doesnt benefit from that, i believe
<clever> yeah
<clever> its more about allowing an EL1 kernel to run in hypervisor EL2
<clever> so you dont pay overheads, where you run linux+kvm in EL1, then have a shim in EL2 that has to proxy every action
<gorgonical> I need to get my kernel running in trustzone and am faced with either using qemu and faking it or figuring out how to host it myself
<gorgonical> my board doesn't have v8.4 so I can't use one of the secure hypervisors out there
<clever> the rpi does allow you to run arm code in EL3
<heat> #ifdef CONFIG_ARM_EL1 #define EL_ "EL1" #else #define EL_ "EL2"
<heat> gg
<heat> i have solved arm and world hunger
<clever> heat: but a `#define EL1_` cant change EL1_FOO into EL3_FOO
<heat> msg me and i'll give you my paypal, I only take EUR
<heat> man
<heat> s/"EL1_/EL_"/g
<heat> I'm expecting 200 EUR by the end of the day
<clever> heat: #define still cant replace on a partial match, only whole-word matching
<heat> EL_"TTBR1" will work as you want it to
<clever> heat: except assembly doesnt want the register quoted
<heat> it expands into "EL1_""TTBR1"
<heat> assembly is probably not your biggest concern
<clever> orr r8, r4, #MMU_TTBRx_FLAGS
<heat> (.S that is)
<clever> arch/arm64/mmu.c: ARM64_WRITE_SYSREG(ttbr0_el1, ttbr);
<clever> heat: ah, aarch64 lk is using defines like this more, that might be able to do something...
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<geist> gorgonical: i wasn't, but it is quite easy to get it running in trustzone
<geist> clever is not exactly right: running in secure EL1 looks exactly like regular EL1
<geist> EL2 and EL3 is not the same thing
<geist> but then it depends on what you mean by 'trustzone'
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<gorgonical> I'm mainly wondering about the el3 component you need
<gorgonical> The docs are a liiiitle bit sparse about it and describe a tlk dispatcher component that lives at el3
<clever> geist: i assumed he meant EL3, but i can see how secure EL1 would be far simpler
<gorgonical> yeah, I just need to get it running in secure EL1
<geist> ah that's a case where i'd use the standard stuff that ARM makes
<gorgonical> like the trusted firmware chain?
<geist> open source, easily portable, etc
<geist> well specifically their repository of code, the name blanks me
<geist> but they have a specific EL3 implementation that's basically the default solution
<geist> most socs use it
<geist> but among other things it implmenents the BL31 EL3
<gorgonical> right. That's what I plan on doing but you need some kind of dispatcher that allows the el3 firmware to interface with your sel-1 kernel
<geist> that's what it implements
<gorgonical> is there a generic one? the readthedocs say that each trusted OS supplies its own dispatcher that you specify when you build bl31
<geist> the BL31 component of it stays behind in EL3 and does the dispatch according to their documented one
<geist> yes! that's exactly what i'm telling you
<geist> they provide BL31, the mechanism to commonicate with it is documented and standard
<geist> whatev3r oses exist in EL1 to comms with it need a driver for it
<gorgonical> oh. well I guess I should read this more carefully then. I must be misunderstanding how this bl31 driver gets written
<geist> i dont know precisely what it looks like, and it's probable its a substantial amount of work
<geist> but at least it's there
<geist> i dont know either, but clearly it's there
<geist> anyway, gotta go, meeting time. actually a block of meetings all afternoon. yay wednesday
<gorgonical> I am sure it is. thanks for the help!
<geist> well, i mean the interface may be documented, the mechanism and how you're supposed to use it may be implied
<geist> and thus not documented
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<heat> geist, isn't it arm64 that has specific instructions for kernel-user loads and stores?
<heat> or am I confusing it with something else
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<mykernel> i am getting gpf (error 0x18) in userspace on iretq (in timer irq)
<mykernel> i suppose my mistake lies in gdt because i had to setup gdt like this for syscall/sysret to work:
<mykernel> add_gdt_entry(0, 0, 0, 0, 0);
<mykernel> ONLY ON AMD CPUS (on hardware)
<mykernel> add_gdt_entry(1, 0, 0xfffff, 0x9a, 0xa); // code ring0add_gdt_entry(2, 0, 0xfffff, 0x92, 0xc); // data ring0add_gdt_entry(3, 0, 0xfffff, 0xf2, 0xc); // data ring3
<mykernel> add_gdt_entry(4, 0, 0xfffff, 0xfa, 0xa); // code ring3
<mykernel> add_gdt_tss(5, (uint64_t)&tss, sizeof(tss_type), 0x89, 0);
<mykernel> PS. syscall/sysret works everywhere but when irq happens in usermode on amd cpus i get gpf
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<heat> it's syscall and sysexit btw
<heat> wait
<heat> no
<heat> my bad
<heat> it's syscall and sysret, sysenter and sysexit
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<heat> not confusing at all!
<mykernel> any ideas what it could be?
<mykernel> working on every vm, and every intel cpu, but not working on any amd cpu
<mrvn> what instruction does it fail on?
<zid> Oh, I figured out why my jpegs were fucky on wookiepedia
<zid> they were JPEG-XLs
<zid> and my decoder needed updating
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<heat> zid, what were you doing on wookiepedia
<mykernel> mrvn: on iretq
<mykernel> returning from interrupt
<heat> what's the error code
<mykernel> gpf, error code is 0x18
<mykernel> you have everything 10 messages above
<heat> what the iretq frame before iretq'ing
<bslsk05> ​github.com: Onyx/boot.S at master · heatd/Onyx · GitHub
<mykernel> i cannot have gdt in this order because of syscall/sysret:
<mykernel> user cs
<mykernel> kernel cs
<mykernel> kernel ds
<mykernel> user ds
<mykernel> i have swapped user cs and user ds order
<mykernel> amd manual (page 178): If
<mykernel> this field + 8, regardless of the target mode.
<mykernel> SYSRET is returning to 64-bit mode, the CS selector is set to this field + 16. SS.Sel is set to
<heat> yes you can sweetie
<heat> this is the "canonical" GDT order for syscall and sysret
<zid> code data data code makes me made
<zid> mad*
<zid> intel are poofaces
<heat> its null code data code data code data tss
<heat> as it should be, it's in the bible
<mykernel> why 3 times code data
<heat> 32-bit segments
<zid> heat: nope I use code data data code
<heat> it's exactly why syscall and sysret is layed out in that way
<heat> zid, you said that makes you mad
<zid> yes
<heat> well, there you have it
<heat> code data code data code data
<heat> gl hf paypal me 50 eur by the end of the day
<heat> you even get the pleasure of 32-bit
<mykernel> syscall/sysret works great but the problem lies in this gpf that occurs only on amd cpus and i cant fcking figure out whyy
<heat> i dont care
<heat> swap out the gdt
<heat> and test it
<mykernel> dude i do not see how i can swap it
<heat> how
<zid> Target code segment — Reads a non-NULL selector from IA32_STAR[63:48] + 16.
<mykernel> data needs to be cs+8
<zid> Stack segment — IA32_STAR[63:48] + 8.
<heat> and it is
<zid> syscall uses 0 and +8, sysret is +16 and +8
<mykernel> you mean i need to use 32bit data and 64bit code
<heat> no?
<mykernel> zid seems to be only one who gets it
<heat> wrmsr(IA32_MSR_STAR, (((uint64_t) ((USER32_CS) << 16) | KERNEL_CS) << 32));
<zid> unless 32bit, in which case 0 and +8 again
<zid> so if you're *not* doing 32bit, the code data data code ordering makes sense
<mykernel> im only doing 64bit
<heat> a 32-bit data segment is also not a thing
<zid> but if you're doing 32bit you want [code data] [code (data] code) or something
<heat> listen, you want a GDT that works, here's a gdt that works, test it if you fancy it
<heat> I don't care if you have issues understand how this works, it does work
<heat> understanding*
<zid> so does code data data code, for pure 64bit, heat
<heat> I've been giving you suggestions for the past day and you've been silently discarding them
<heat> zid, ok great
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<mykernel> atleast zig gets me
<mykernel> zid*
<geist> heat: yeah, re kernel-user load/stores arm32 and arm64 has them
<geist> basically it's a ldr and str with user permissions
<geist> youc an even use them in user space if you want, it just doesn't do anything there
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<gog> hi
<zid> tooth brush.
<Bitweasil> Yeah, LDRT/STRT, I think?
<kaichiuchi> hi
* gog brushes zid
<zid> with a brush made of teeth?
<kaichiuchi> can someone drop me about $50 million so I can retire early
<kaichiuchi> and dedicate a good portion of my time to programming
<gog> zid: are you danhausen or smth
<kaichiuchi> thanks, the return on investment will be great
<Bitweasil> kaichiuchi, you don't need $50M to retire and hack.
<kaichiuchi> you're right
<Bitweasil> Just go find somewhere rural and cheap. $110/mo for Starlink solves a lot...
<gorgonical> kaichiuchi: I can provide better investment than him. Give me like $500,000 and I'll be happy
<gorgonical> I already live on $30,000/year. Just give me a house and that stipend and I'm golden
<gog> give me $5 and i'll do anything you want
<zid> For $500 I'll give you 2 hours of work
<gorgonical> not even enough for one whole gullfoss
<gog> :D
<kaichiuchi> i am trying to do something crazy at my job
<kaichiuchi> moving us from IAR to LLVM
<kaichiuchi> how many of you think they'll go for it raise your hands
* kaichiuchi does not raise his hand
<gog> oof
<Bitweasil> If your job is driving a bus, well... probably nobody cares.
<gorgonical> bisqwit vibes huh
<kaichiuchi> well, I'm just stunned that people are still using IAR after all of this time in the embedded world
<kaichiuchi> intel uses LLVM, ARM uses LLVM/GCC
<kaichiuchi> why would you spend obscene amounts of money at this stage on compilers *anyway*, regardless
<kaichiuchi> maybe if you're in some safety critical field where a compiler has to be certified, sure
<kaichiuchi> but, we are not
<gorgonical> The thing I actually want is a time chamber so I can do more work per day whenever I like
<gorgonical> And not tell anyone
<kaichiuchi> what do you do that you make $30k/yr? retail?
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<kaichiuchi> if so, I've been there
<gorgonical> phd student lol
<kaichiuchi> oh
<Bitweasil> A damned well paid one. :P
<Bitweasil> Back in my day, PhD students were paid peanuts! And not them fancy new canned ones, they were cafeteria floor sweeping peanuts! :p
<kaichiuchi> i never went to college
<kaichiuchi> i couldn't afford it
<gog> neither could i but i did anyway
<kaichiuchi> and I slacked off in high school
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<kaichiuchi> so I was considered a dummy
<gog> now i have lots and lots of debt
<gorgonical> Bitweasil: I get very good healthcare, too. People shit on my university but my advisor is good and I feel like broadly the school has been good to me, also
<kaichiuchi> gog: it's that situation that i would like to avoid at all costs
<gog> it's a smart plan
<kaichiuchi> i mean, the fact that I got in anywhere without a degree was after quite literally 10 years of begging every company I could find
<gog> community colleges are fine too
<gorgonical> kaichiuchi: I went to a very shitty in-state school and was able to get out of it debt-free. I made a very large upgrade in quality from undergrad to grad
<Bitweasil> ^^ Yeah, if you're planning on grad school, get your undergrad cheap and usually grad positions have some way to pay the way.
<kaichiuchi> yeah I considered doing community college/shitty in-state school
<Bitweasil> Research assistanships or something.
<gorgonical> That's exactly what I did. RA for 1.5 years after bachelors and that was enough to open the door for a better school
<kaichiuchi> what I do know for sure is that if I had done better in high school and went to college _somewhere, anywhere_, I probably wouldn't have been in retail for 10 years
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<gorgonical> It wasn't even in what I researched. I did networking research and moved into OS
<kaichiuchi> i'll tell you all a secret: I did in fact go to community college for a semester and promptly dropped out after hearing the professor talk about windows XP in 2014
<kaichiuchi> and by "talk about" I mean half of the course material was windows XP
<gorgonical> lord almighty. Reminds me of my undergraduate os course, where we used java
<kaichiuchi> i was a fool
<kaichiuchi> i should've stayed
<kaichiuchi> no matter how stupid the material was
<zid> I think I was using xp in 2014
<kaichiuchi> you're also a very strange dude
<Bitweasil> I mean, what's wrong with XP? By SP3, it was a decent enough OS, and if you're doing OS fundamentals, I see no real problems with it.
<Bitweasil> It's a lot simpler than Win7/Win10, especially in driver models.
<kaichiuchi> Bitweasil: the course material said that windows XP was the latest OS.
<zid> and?
<kaichiuchi> aaaaaaaaaand that meant it was outdated by a considerable measure
<zid> no?
<kaichiuchi> what?
<Bitweasil> A deck I saw from the Com Sci department claimed Linux was written by "Linus Torvaldo."
<gog> windows XP is the latest OS that doesn't suck
<zid> tech basically hasn't changed noteably in 20 years tbh
<kaichiuchi> windows XP was _not_ the latest version of windows at the time in 2014 I can promise you
<Bitweasil> If it's an OS foundations course or something, there's basically nothing new under the sun.
<Bitweasil> It's just way more complex now.
<Bitweasil> ... again, so? How was the rest of the material?
<kaichiuchi> it wasn't an OS fundamentals class
<kaichiuchi> it's not at all a programming course
<zid> "My french textbook is from 2014, fucking outdated shit"
<Bitweasil> *shrug* Ok.
<Bitweasil> Le crap!
<zid> that's what you sound like to me
<kaichiuchi> it was a "this is a keyboard, this is a mouse, this is how you use a mouse, this is how you type on a keyboard" course
<Bitweasil> Yeah, I'm with zid here. If the rest of the material is *correct,* who cares what it claims is the latest OS?
<gorgonical> Okay an interesting question: do we still teach x86 in OS class because of its dominance?
<zid> did we start doing that at some point? :P
<gorgonical> It continually introduces this ugly 32/64-bit division that people like dh` avoid because 32-bit is hard enough
<Bitweasil> gorgonical, I would say if you're doing anything in the OS space, you *should* know x86, but... also, yeah, I think I learned OSes on MIPS and PowerPC stuff, because it *didn't suck.*
<zid> I thought everybody used fictional edutainment systems like MIPS for everything
<Bitweasil> Hey now. SGIs weren't fictional. :p
<kaichiuchi> i like MIPS :(
<Bitweasil> And the R10k was a serious asskicker at the time.
<gorgonical> I used MIPS for my assembly and hardware classes, but x86 for actual OS structure
<zid> They were outside of n64 dev kits
<zid> tbh you can do 99% of OSdev stuff inside usermode on your desktop
<zid> it's only the two instructions to actually swap the page tables etc that matter compared to real hw
<Bitweasil> I hate to say it, but you should be learning OS fundamentals independent of the architecture. There's some value for how it maps down onto the ISA, but if your OS design is fundamentally hardware-focused, you're down the wrong path for college courses.
<zid> mmap a gig of memory and write your allocator against that
<zid> etc
<zid> way easier to test, too
<Bitweasil> Yeah.
<Bitweasil> You can use a proper debugger.
<Bitweasil> And get reasonable segfaults if you do something stupid instead of scribbling on your NIC.
<gorgonical> Bitweasil: of course. That's actually what my OS class did: java-based pieces. But a lot of projects use qemu/bochs as the testbed so the ISA is a necessary consideration
<Bitweasil> <3 Bochs.
<clever> Bitweasil: on that subject, i once saw somebody translate a windows driver into a linux elf.so, and stub out all of the imported symbols, so he could gdb it
<Bitweasil> Extended it to support the SMM hypervisor back in the day.
<Bitweasil> Alright I need to roll for the evening.
<Bitweasil> later!
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<kaichiuchi> bye
<gorgonical> I was at a conference recently and caught an itch to write some risc-v chips with like chisel or something
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<zid> gorgonical: Did you get the cream you needed to fix it?
<zid> Scratching itches is bad
<gorgonical> I didn't, but I do have itch cream for my regular itches
<gorgonical> It's one of those projects that I'm pretty sure I could do, but the scale of it is wholly unknown and I have lots of projects already
<zid> Warning: RISC-V may cause severe itching, sensations of falling, loss of vision, delusions of grandeur.
<gorgonical> I attended a talk where the main take-away was: "risc-v is inevitable"
<zid> If what you care about is "crap micros" then yea that sounds like it might be true
<gorgonical> I almost have finished a risc-v asm project and the last time I mentioned it someone said the thought made them ill
<gorgonical> lol
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<zid> Oh I should add that to the symptoms, nausia
<zid> nausea
<kaichiuchi> do people actually care about RISC-V?
<gorgonical> in supercomputing, quite a lot
<zid> some people have a huge hardon for it as though it's some amazingly performant high concept ISA that will upend the tech world
<zid> so most of the chat is either those people, or me making fun of those people
<zid> in reality? It'll replace some 8051s and once it's a bit more mature and someone is selling full designs it might save you a cent or two per part
<zid> and people will try weird things with it just because it's new, like taping a few thousand together
<gorgonical> the research story for it is hugely different
<gorgonical> being able to try out some wacky hardware architecture is really valuable right now. Especially with the accelerator side of hardware becoming more dominant, risc-v controllers are already prevalent there
<zid> What it is in reality is a very very basic teaching ISA
<gorgonical> Even if they aren't the application cores, they are already being used as the controllers
<zid> (like a 8051)
<zid> Best way I can compare risc-v to another chip would be like, what if you took the design ideals of a 6502 'Run modern software using as few gates as possible', and made it for the 90s+ so that means 32bit etc
<zid> people can throw extra gates at it later to make it faster if they want, or keep it as-is and make it a 1 cent part
<zid> that runs like ass but at least can run softawre a C compiler psat out
<gorgonical> right, but what people like so much about it in research is that it's open source and actually good enough to use
<gorgonical> we've had the other riscs in the past, ofc
<zid> yea it's designed for that, literally
<zid> it's a teaching ISA
<gorgonical> I don't agree. There was a really interesting paper about how to hack the vmcall mechanism to accelerate ipc
<gorgonical> And then they showed that you could easily implement this engine with risc-v and the rocketchip on fpga to actually evaluate it
<zid> you disagree it's an educational ISA *because* people are writing papers about it?
<gorgonical> not about it, *with* it
<zid> you disagree it's an educational ISA *because* people are writing papers with it?
<gorgonical> I don't agree that the utility is in teaching people about ISAs. it is useful for that, but I feel like calling it educational hems it in and means you can't learn anything novel with it
<zid> research ISA then if you want
<gorgonical> that I can fully agree with
<zid> same thing to me, but if you prefer one of the other we can go with that no skin off my nose
<zid> s/of/over
<gorgonical> I don't mean to be pedantic but I think there's a big difference at least in how we think about it
<gorgonical> If all it's ever useful for is finding instructive insight that can be applied to e.g. arm then that's still very interesting to me
<zid> open things are nice, this isn't new
<zid> lots of tech explosions have happened because certain things have been opened (see: unix)
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<gorgonical> yeah, and risc-v is the opening of hardware, and this one (seems) to be sticking
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<gorgonical> the fact that you can deploy designs to fpga-accelerated cloud services for evaluation is making a lot of companies and labs excited
<zid> I mean technically all this stuff was psosible before, but it's acting as a lingua franca
<zid> you're not doing it on some random in-house design nobody cares about and you might not have the rights to release enough info about to write a useful paper
<zid> but now everybody can write papers about the same thing
<gorgonical> yeah. I'm not as into accelerators but there was a good argument made by the sycl people that having a common ISA at the bottom makes it a lot easier to optimize software stacks
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<Clockface> is risc V being adopted for general purpous computers too?
<Clockface> or is it more for specialized things that need to be programmed
<mrvn> Clockface: what's a general purpous computer?
<Clockface> the manufacturer doesnt fully know what its going to be used for
<Clockface> and it isnt specialized too much
<Clockface> PC's and i feel like rasberry pi's fall into my definition too
<Clockface> are what come to mind
<mrvn> every computer falls into that definition. Nobody build special purpose computer except maybe for space.
<Clockface> microcontrollers they know are going to be used to control something physical though
<gorgonical> as far as I can tell risc-v is mainly being used in the controller space and in application-specific cases
<gorgonical> The advantages risc-v has aren't really at being as fast as x86 or even arm64 at this point
<mrvn> certainly not on an fpga
<gorgonical> certainly