<bslsk05>
github.com: Onyx/kunit.cpp at master · heatd/Onyx · GitHub
<bslsk05>
github.com: Onyx/elf.cpp at master · heatd/Onyx · GitHub
<heat>
it's super basic googletestie, you can't really notice a difference
<mrvn>
heat: I don't quite get something there. On top of page 10 they show a superblock where the missing chunk is in the middle. But earlier they said they always split superblocks so their blocks are sorted by size.
<mrvn>
heat: how do does the sorted superblock devolve into a scrambled one?
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<moon-child>
o hai DjanSeriy
<moon-child>
when did you get here
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<heat_>
mrvn, dunno, I haven't digested it properly
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<heat>
you know, I was thinking way too long about making a DAG for my bpf interpreter when detecting a loop really is trivial
<heat>
I can get by using a bitmap executed[N] and if executed[jmp_dst] == 1 this is a loop
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<heat>
akshually, this may not 100% work, I may indeed need a CFG
<heat>
yeah my idea goes to poopy with actual conditionals
<heat>
not that I'll get a CFG for this since its just cBPF, I can get away with a halfassed approach and cross muh fingers
<bslsk05>
sandpile.org: sandpile.org -- The world's leading source for technical x86 processor information.
<gamozo>
Nearly everything on sandpile (eg. in those specific diagram shapes) can be found in the SDM, but sometimes they're tucked in a footnote or something.
<gamozo>
sandpile is bae for quick ref
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<geist>
i discovered the other day that the sandpile guy works at google
<geist>
i mentioned t to someone and they're like 'oh yeah XXX he's over in YY'
<heat>
everyone works at google
<heat>
it's a massive conspiracy
<mrvn>
heat: what do you need a buddy-allocator for by the way?
<heat>
page allocation
<mrvn>
as in physical pages?
<heat>
yes
<mrvn>
Do you have hardware that dynamically needs contigous physical pages?
<heat>
yes
<heat>
I also need large pages
<heat>
and bigger chunks of physical memory is useful for the slab allocator
<geist>
woo hoo short 1 minute power out
<mrvn>
on the one hand I get large pages, but they are 9 powers of 2 larger so buddies maybe aren't the best way to go about them.
<mrvn>
on the other hand they are 9 powers of 2 larger, fragmentation will be hell and eventually you run out and need some other mechanism to get large pages.
<mrvn>
Except maybe on ARM where you have sizes between page table levels.
<mrvn>
have you considered using recursive slabs? Have a slab for all memory containing 1GB objects. From that you allocate to populate a slab for 2MB objects and from that a slab for pages.
<heat>
hm?
<mrvn>
or in other words a generalized buddy allocator using a 512-way split.
<heat>
ok so you want a buddy allocator?
<geist>
just wants a buddy
<heat>
that's what the allocator is for geist
<heat>
page tinder
<heat>
i have realised my jit problem is going to get a lot more complicated
<mrvn>
me? not exactly. I would use more the slab data structure handling each level separately. What I don't think is best is the 2-way split of a plain buddy system. A 512k block of memory does you no good.
<mrvn>
(unless you have some hardware that needs such blocks)
<heat>
BPF programs on packets expect loaded data to be endian-reversed...
<heat>
except seccomp ones don't
<mrvn>
heat: In your page tinder half the deallocations will swipe right and the other half swipe left. Aeh, I mean merge.
<mrvn>
endian-reversed? As not network byte order?
<heat>
yup
<mrvn>
heat: don't they expect host byte order?
<heat>
well, that is reversed
<mrvn>
only on some archs
<heat>
on most sane archs
<mrvn>
not sure I would call m68k, mips, arm, ... insane
<heat>
arm is le
<mrvn>
arm is biendian: "Modern ARM processors support a big-endian format known architecturally as BE8 that is only applied to the data memory system."
<heat>
so optionally LE so you have no reason to use BE
<mrvn>
geist: do you know of anyone using ARM in big-endian mode?
<heat>
some routers maybe
<geist>
i've heard of it mostly in the networking space
<mrvn>
For network hardware it makes sense to run in network byte order, makes sense.
<geist>
i guess linux kernel has support for it and i guess you could compile a armbe debian or something, but haven't personally seen it
<heat>
nitpick: annoying there's no explicit bswapw
<geist>
a 16 bit swap you mean? I thought there was
<geist>
there's also a bit swap which is pretty neat
<heat>
no, there's no 16 bswap
<heat>
you need to use xchg %lower, %upper
<geist>
sure, i guess a 32bit bswap plus shift is what you need
<mrvn>
On x86 they would have replaced one of the smaller sized opcodes to mean the bigger size in long more.
<mrvn>
stupid mode specific default size and size prefixes.
<geist>
nah what arm32 generally does is all instructions have a 32 and 64bit version (usually just a bit that sets the operand size) and then in the case of shift and rors 6 bits are allocated in the opcode
<geist>
s/arm32/arm64
<geist>
think of arm64 is mostly a superset of arm32 however the tricky bits like conditional instructions and barrel shifter on the seconmd arg is gone, those bits are used for more opcodes/etc
<geist>
also FWIW arm64 does have a 16bit byteswap: REV16
<mrvn>
Note that ARM doesn't seem to have a 8bit rotate
<geist>
course not. doesn't operate sub register like x86.
<geist>
arm64 however does have 32 and 64bit versions of most stuff. that's a conceit to make it a bit easier to run 32bit stuff
<geist>
not all risc machines have that sort of consideration
<mrvn>
it's not really subregister in x86, they just have a register for every size
<geist>
generally arm64 cdoes it because it's condition register based. so you may want a add32 or add64 to set the condition bits based on what is considered the target size
<geist>
whereas arches like riscv or mips that dont have condition registers you generally dont need that sort of thing
<mrvn>
You also have a lot of code that simply needs just an "int" and it might be faster.
<geist>
yah. arm64 is fairly pragmatic in that regard
<mrvn>
They could have added CC32/CC64 registers. Just one "add" but on "cmp" you then pick which flags to use.
<geist>
that's a good pdf btw, you should save it
<geist>
really sums things up well
<mrvn>
Oh, that's just 3 pages cheat-sheet. Got to print that next time I'm at a printer.
<geist>
huh things i didn't knmow about: EON, ORN: xor and or with negated second arg
<geist>
not sure i've ever seen the compiler emit that, or the disassembler tends to replace that with EOR of the negated constant
<mrvn>
assuming you have a constant
<geist>
yeah with a register i guess i've just never seen the compier usei t
<geist>
kinda curious now...
<mrvn>
Aren't there lots of constants that couldn't be expressed in the opcode negated? x ^ const should do "x EON !const" when that allows an immediate.
<mrvn>
When I loose power no amount of backup normaly helps. I might still have power but the next hop upstream will shut down so I'm offline anyway.
<geist>
i have a fewbattery backups to ride my computer and the core switches/cable modem over till the backup generator kicks
<geist>
but usually i wait about 10 minutes and if the power isn't coming back i start to power everything off
<geist>
and then turn off the generator
<geist>
and yeah usually after about an hour i've discovered the cable modem network usually goes down. probably some battery backup somewhere upstream in some remote note
<geist>
node
<geist>
heat: also if the power lines were written in RUST there wouldn't be this problem
<zid>
heat: let's have an increment contest, who can write an increment in the fewest characters
<heat>
my neverending set of defines whose meaning is clear to me and me only
<heat>
also very funny how there's a specific opcode for AND EAX
<geist>
yah think of AX as the accumulator
<geist>
it's the thing you should be doing work in, the other registers are there to hold temporaries or for other purposes (base register, counter, etc)
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<geist>
it's of course totally opposite of how you should use registers nowadays, but if you come from a world of 6502 or whatnot where the accumulator is *the* register it makes sense
<zid>
we should replace the short encoding for and rax with and rsp
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<moon-child>
what's cursed about that code? Looks like pretty par for 'ghetto'-style assemblers (as opposed to proper table-based ones)
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<DjanSeriy>
moon-child: idk maybe a few weeks back
<gog>
hi
<moon-child>
sup
<Ermine>
hi gog!
<gog>
:)
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<Ermine>
gog: may I pet you?
<gog>
yes
* Ermine
pets gog
* gog
prr
<Ermine>
aww
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<kaichiuchi>
...i think i need to go back to sleep
<kaichiuchi>
god C++ makes life fucking *annoying* sometimes
<kaichiuchi>
why is type punning through unions undefined behavior :(
<jafarlihi>
Someone please do the needful and help. In here: https://stevemorse.org/8086/29.jpg the instruction at the top says it is to DI register, but onlinedisassembler.com says it is to BX register given same bit pattern. Which one is true?
<jafarlihi>
Here's the bit pattern by the way: 0xc7070ff0
<jafarlihi>
shell-storm.org also says BX
<jafarlihi>
Is it wrong in the book?
<kof123>
from the middle of the page: figure 2.23 moves 1111 0000 0000 1111 into a word in memory in the data sagment at the offset contained in DI
<kof123>
so what do you mean "to DI register" ?
<kof123>
note it talks about figure 2.21, which is not at the top of the page, and presumably a page or so back
<bslsk05>
onlinedisassembler.com: ODA - The Online Disassembler
<GeDaMo>
If you select i8086 it does say bx
<gog>
hm
<jafarlihi>
One more thing, in here: https://stevemorse.org/8086/28.jpg Fig 2.21 says that instruction moves the immediate to the register. In Fig 2.23 however, it says it moves to offset specified by the register. For other instructions, how would I go about knowing whether it is like the former or the latter? Is there some kind of letter associated with differentiating that behavior?
<kof123>
C707F00F mov word [bx],0xff0
<kof123>
C7050FF0 mov word [di],0xf00f
<kof123>
quote ndisasm
<gog>
objdump gives me bx, i think that's what onlinedisassembler is using on the backend
<jafarlihi>
So objdump bug then?
<gog>
no because it's consistent with ndisasm
<gog>
maybe the book is wrong
<gog>
c705 gives me mov indirect via di
<jafarlihi>
What does c7070ff0 get you?
<jafarlihi>
That's what's in the book
<gog>
bx
<jafarlihi>
But ndiasm bx is c707f00f, not c7070ff0
<kof123>
if thats from my quote, ignore that, that is just me in a hurry
<gog>
the immediate is the lower word
<kof123>
^^
<jafarlihi>
Ok, thanks
<gog>
the instruction is encoded in c707
<gog>
OPCODE 11000111 -> C7
<gog>
mod opcode r:M 0000111 -> 07
<gog>
00000111*
<jafarlihi>
One more question, if in the same instruction "w" is 0 then immediate will be 8 bits right? But what about the register in modr/m, will it be 8bit too?
<gog>
yes
<gog>
it does a movb
<jafarlihi>
If so then the question is how is segment:offset is calculated with 8 bit register, doesn't it require 16 bit segment and 16 bit offset?
<gog>
the register, hwoever
<gog>
is still 16 bits because it's an indirection
<gog>
the immediate has to be 8 bytes'
<jafarlihi>
so sign extended then?
<gog>
because its encoding is only 3 bytes
<gog>
no it's not sign extended, the immediate has to be only one byte
<gog>
the address is already in the register
<gog>
you're moving to the memory location at the address in the register
<jafarlihi>
But how is effective address calculated? If the register is 8 bits too, doesn't it require 16 bit offset?
<gog>
no, teh register is not 8 bites
<GeDaMo>
The immediate is 8 bits
<jafarlihi>
Oh, okay
<jafarlihi>
Thanks
<gog>
you have to prepare the address register before an instruction like this
<gog>
and without a prefix override it'll be es:(destination op)
<jafarlihi>
You mean ds
<GeDaMo>
In the Intel manuals, modr/m of 07 is [bx] in 16 bit mode, [edi] is 32 bit mode
<gog>
no, writes go to es: iirc
<gog>
but i might be wrong i don't play with real mode anymore
<GeDaMo>
Volume 2, table 2.1
<jafarlihi>
Is Intel manual known to contain many errors?
<gog>
it's a huge manual
<gog>
it might have been an oversight by the author and editor alike. the author was thinking about protected mode operand encodings and thought it was 1:1 with real mode
<jafarlihi>
Will try to get 8086 assembler then upgrade it all the way to x64
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<Arsen>
.code64 :^)
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<heat>
sup nerds
<GeDaMo>
I got Covid and Flu vaccinations
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<heat>
my last covid vax was a year ago or so
<GeDaMo>
Same, this is the latest booster
<heat>
moon-child, if you decipher what MOVstli32 means without checking the opcodes I will be most impressed :P
<heat>
I could use some generic mov_load() that could take registers and addends and that shit and generate an opcode in a less-specific way
<heat>
new idea: what if we created a simple ISA where instructions just operated on registers, fixed size instructions, and then load + store instructions which operate on memory? None of this modrm debauchery with creative addressing
<GeDaMo>
It'll never catch on :P
<heat>
we could call it HISC for heat's instruction set computer
<GeDaMo>
HEAL: Heat's Elegant Assembly Language
<heat>
HARM: Heat's advanced resourceful machine
<GeDaMo>
HUNT: Heat's Unique New Technology
<heat>
HEAT: HEAT
<heat>
hearing americans pronounce muller is something else
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<heat>
almost as good as how they say tortillas
<gog>
tortiyas
<GeDaMo>
torTEEah
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<gog>
when i'm making them they're tortiyaaaaas queen
<GeDaMo>
(I have no idea :P )
<heat>
you mean tortilas
<gog>
torTILLas
<heat>
or tehcos
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<gog>
tAYcos
<gog>
yo quiero taco bell
<heat>
no señorita, no hay taco bell en IRC
<heat>
gog, buy a germany jersey and go to work with it tomorrow
<gog>
lmao
<gog>
the CEO would be pissed
<gog>
i'm gonna do it
<gog>
where can i get a germany jersey before 9am tho
<heat>
adidas
<heat>
the gog gets fired for epic trollage
<DjanSeriy>
getting fired Any%
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<GeDaMo>
Maybe you could wear a combination of the German colours
<gog>
i don't have any yellow
<gog>
ooh oooh
<gog>
i can do my eyeshadow in geermany's colors
<gog>
yaaaaaaaa whooooool Königin
<heat>
este equipo no juega una mierda
<heat>
at least I got a proper english stream
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<zid>
does he think he's going to be born somewhere else all of a sudden
<zid>
"better make sure they know I'll be english for a while"
<zid>
Breaking news: 42 year old kitchen fitter Mark Harris from Brighton (pictured) has been given birth to by a Dutch mother of 2 (now 3). Mark Harris is said to be "gutted" to no longer be English.
<heat>
huh
<heat>
confused.jpeg
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<mjg>
look at this long name mofo
<mjg>
cnfsd.jpg
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<mjg>
there, dos-frienly
<heat>
shut up
<heat>
no one cares about dos
<heat>
it's all about this "UNIX" these days
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<zid>
mr mouse snuck out of my room while I was getting a drink, he's scratching the door to be let back in..
<zid>
kinda cute seeing his little paws through the crack in the frame
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<heat>
what the actual fuck
<gog>
aw
<gog>
tiny rodent
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<heat>
what's the functional difference between mul and imul?
<zid>
imul is signed
<zid>
mul is unsigned
<heat>
thanks fuckboy
<heat>
but what does that functionally mean
<zid>
range
<heat>
ELI5
<heat>
gcc appears to use imul for unsigned int multiplication
<gog>
imul is effectively the same in one form
<gog>
but the two other forms are not the same
<gog>
unsigned multiply has no equivalent encodings
<heat>
I know, I just want to know what the actual difference is
<heat>
is it just a matter of eflags?
<gog>
intermediate product
<gog>
idk
<gog>
it basically seems to be about the fact that there are more encodings for imul becuause you can specify a destination operand
<heat>
the amount of different encodings gcc has for multiplication is insane
<heat>
it's pulling lea's with adds and shit
<geist>
signed vs unsigned mul/division is not like 2s compliement arithmetic
<geist>
the sign bit has to be handled explicitly (though not hard)
<geist>
but that's why you always end up with two different opcodes on pretty mcuh all arches, even riscv
<heat>
so why is (unsigned int) * (unsigned int) = imul valid?
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