<bslsk05>
github.com: Can't get the package list · Issue #219 · klange/toaruos · GitHub
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<klange>
excitement*
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<zid>
I have absolutely no idea how to download things on github anymore
<klange>
Release are straightforward, CI artifact builds require you to be logged in because the CDN access involves a time-cycling token issued only to logged in API users. Repo downloads have remained "here's a ZIP, good luck" for years (which I've always hated, it's a fucking git repo, give me a tarball of some sort!)
<zid>
what's the root password I forget
<zid>
It's on the right bar now, under a random amount of shit, re 'releases'
<zid>
instead of at the top where it used to be
<klange>
Yeah they moved it out of the tabs, and the keep shoving other stuff up there I don't care about
<klange>
Like dependency alerts. I have no dependencies, get this shit out of my face!
<zid>
seriously though what's the root password
<zid>
I need to run the sudo
<zid>
default user's is local I think?
<MelMalik>
klange: do you irc from Toaru?
<zid>
thanks readme, that works cus sudoers
<klange>
MelMalik: not regularly, no
<MelMalik>
oh
<klange>
zid: `local` is the password for `local` which is the account the Live CD automatically logs into.
<zid>
okay so networking appears to work my end on the 1.99.8 at least
<zid>
(i'd not tried networking before)
<klange>
2.0's (1.99.x's) net stack is brand new, and while it's still terrible it is much improved in architecture over the one in 1.x
<zid>
hmm, if I deselect everything on the desktop, right click still gives 'edit in bim' for the previous selection
<klange>
Ah, yes, someone was annoyed by that... I should add a disabled state to menu entries, that's probably the best fix.
<klange>
I guess I could show a different menu if no files are slected...
<klange>
I just don't want to dynamically generate the context menu because ugh :\
<zid>
rip, no tls for `fetch`
<klange>
You need the `fetch-tls` package which pulls in mbedTLS.
<klange>
At least until I stop being scared of big numbers and actually write a TLS3 implementation.
<kazinsal>
I'm pretty firmly in the NIH train but I think I'm going to just defer to OpenBSD for my SSH and TLS implementations
<kazinsal>
"don't roll your own crypto" is a good mantra; doubly so for anything publicly internet-facing
<zid>
how do I set my keyboard locale I forget
<klange>
You don't / you tell QEMU to convert to en-us with uh... the -k option?
<klange>
(sorry)
<zid>
I don't use en-us
<zid>
in either direction
<zid>
What if I want to type weeb shit
<klange>
No that should convert the keys going *in* to en-us so you can type normally and the vm understands
<zid>
also, not using qemu :p
<kazinsal>
then you write a pull request
<MelMalik>
Is Toaru supposed to be UNIX-like?
<klange>
Ah, dunno if anything else can, and if you're on hardware then oof
<klange>
Yes, it does the basics. File descriptors, process model, strong TTY presence.
<zid>
what's the wallpaper choser called, I think I silently crashed it
<zid>
I wanna run it in a term
<zid>
oh wallpaper-picker that was a nice tab complete
<zid>
`Segmentation fault`
<klange>
ooh run it in dbg
<zid>
dbg okay
<zid>
build_matrix.isra in your jpeg so
<zid>
I think that's lto crap on the end?
<klange>
thanks! can you share the jpeg?
<zid>
idk how to disassemble in this
<klange>
it doesn't have a disassembler because I'm not _that_ awesome
<zid>
oh you wrote it
<zid>
0x42075aa0 is what it gives for the stack frame anyway
<zid>
do we have a hex editor
<klange>
that's the key, zid, unlesss you downloaded it from the package manager or something, I wrote it ;)
<zid>
also, I am playing "first time using vim", `quit`, `exit`, `q`, `die already ffs` with dbg :p
<klange>
or there's <1% chance Mike Gerow at Google wrote it...
<bslsk05>
en.wikipedia.org: Machine-check exception - Wikipedia
<geist>
yep
<MelMalik>
ah
<heat>
the fun part of MCEs is digging through manuals trying to decode it
<heat>
"fun"
<zid>
"Values below 8 indicate a software error. Values above 8 indicate a hardware error." *stares at his MCE with a value of 8*
<MelMalik>
oh noes :D
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<klange>
zid: it took me a terribly long time and a lot of headscratching because none of my (host, Linux) image viewers gave me relevant information, but I figured out why I can't load that jpg
<klange>
(it's not 4:4:4)
<zid>
ooh that's a very strict requirement
<zid>
4:2:0 is like.. standard
<klange>
I also don't support progressive images, but that's trickier; 4:2:0 should be less terrible of a thing to add to this
<zid>
are progressive images not.. easier?
<zid>
or does progressive mean the mipmapy thing
<zid>
and not 'non-interlated'
<klange>
There's a bit more to it, but it is interlaced. It's not so much that it's difficult, but that the other option (baseline) is so much more straightforward.
<zid>
jpeg committee have a lot to answer for on their definition of the word 'progressive' then
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<klange>
It's, uh... I think I you get a bunch of interlaced bits with progressively higher quality, eg. more DCTs applied?
<klange>
So you can load a full resolution piece of garbage and then add more DCT layers to it... and I don't even know what the interlacing is for? But the point is it's more complicated and I currently only support baseline
<zid>
oh so it is the mipmappy thing
<klange>
I spent far too much time thinking I had bugs in my decompressor, but I was just reading the wrong tables at the wrong times~
<klange>
Well no because mimaps reduce physical size?
<zid>
I've used incredibly slow connections/PCs that actually managed to display it
<klange>
anyway I added a bunch of debug code to the library while trying to figure this out and I'm going to reset everything now :D
<zid>
yep done that many times
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<zid>
Just isn't worth it to keep it without a proper debug infrastructure hooked up to selectively compile it in, and the quality of it is bad anyway etc
<zid>
because it's only for VERY low level debugging, typically
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<klange>
I just changed so much trying different things that I cba to go in and see if any of that was actually better (eg. for performance)
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<klange>
So nope, back to the status quo I know before any feature work is going to happen.
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<moon-child>
hmm. I think it's kind of confusing to explain endianness as 'the number 0x12345678 is stored in memory as 0x78 0x56 0x34 0x12, if le'
<moon-child>
because '0x78 0x56 0x34 0x12' is mixed-endian
<zid>
only because it's written in nibbles
<zid>
but stored in bytes
<moon-child>
yeah
<zid>
I explain system as "The order you store the bytes of a thing which is multiple bytes large"
<zid>
it's fairly apparent that there has to be *some* system there
<moon-child>
but maybe easier to start by presenting e.g. big-endian decimal
<moon-child>
and then saying each byte is like a digit
<zid>
You don't need to start with a confusing nibble level example
<zid>
you can do it in decimal yea
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<kazinsal>
2am bad ideas: I'm considering a kernel core rewrite...
<kazinsal>
there's a whole bunch of stuff that will need an unknown and probably unfortunate number of bodges/fixes to go from 32 bit to 64 bit and, having realized that literally none of my target platforms are 32 bit only, I'm wondering if I should start a new 64 bit core and start grafting drivers etc. onto it as I go
<j`ey>
I concur
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<kazinsal>
I think the plan for tomorrow (well, today, but later) will be to crank out a new x86-64 core, then bolt on some of the more generic platform stuff. Sunday will be the kedebug serial console and writing new user mode stuff from scratch (because my previous stuff is unusable at this point)
<kazinsal>
There's not much reason to maintain a 32-bit kernel in 2021, especially when my goal is to target boards for use as firewalls/routers
<j`ey>
kazinsal: how many LOC in your project?
<kazinsal>
mm, good question. probably somewhere around 50-60k
<j`ey>
more than I was expecting
<kazinsal>
networking stuff is complex!
<kazinsal>
doing it *quickly* even more so
<kazinsal>
my next big projects are TCP sockets and network address translation
<j`ey>
is that NAT?
<kazinsal>
yeah
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<kazinsal>
there are a handful of different types of NAT but the important ones are 1:1 NAT and one-to-many NAT
<j`ey>
is NAT like virtual memory for networks?
<kazinsal>
a bit more complex -- 1:1 NAT is basically a series of rules that swap one IP address out for another, and one-to-many NAT or port address translation rewrites the IP and TCP or UDP headers based on a connection table to map a certain public IP address and port pair to a specific private IP address and port pair
<j`ey>
that doesnt sound like 1:many
<j`ey>
it still goes to one thing in the end
<kazinsal>
there are many private IP addresses, but only one public IP address
<j`ey>
sounds complex
<j`ey>
i just use my ISPs router
<kazinsal>
if the router's public address is 1.2.3.4, then a connection from 192.168.1.30:51063 may get mapped to 1.2.3.4:51063 or 1.2.3.4:anything on its way out, then return traffic is remapped on the way back in to 192.168.1.30:51063
<kazinsal>
you're basically maintaining a mapping table of what fields to match on and rewrite
<j`ey>
so it's for routing traffic in your LAN
<kazinsal>
it's the separation between LAN and WAN, yeah
<kazinsal>
and also the glue that makes them interoperate
<kazinsal>
a router doing NAT is in essence a mostly-passive relay server that just swaps fields in the layer 3 and 4 headers based on what it receives from either end
<kazinsal>
and that on its own is enough for hundreds of machines to completely passively (from their point of view) share one public IP address
<j`ey>
makes sense
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<Belxjander>
kazinsal: so primary focus is networking and other things are all extras
<Belxjander>
???
<j`ey>
dunno if they're still around, but yeah, they're writing an OS for firewall/router stuff
<kazinsal>
yeah, my project is a high performance network operating system
<kazinsal>
(I am "still around" in the sense that I am in front of my keyboard, but not 100% around in the sense that I have had many alcoholic beverages and I have a Gretsch over my shoulder and am doing my best Malcolm Young impression along to a concert recording from the 70s)
<Belxjander>
kazinsal: IPv4+IPv6+TCP+UDP+ICMPv2 ?
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<kazinsal>
I haven't done any IPv6 stuff yet
<kazinsal>
mostly because of my experience in the real world of networking
<kazinsal>
I'm a network and datacenter engineer by education and trade, so I have a solid idea of what real world enterprsie networks look like
<kazinsal>
and they are pretty solidly IPv4 throughout
<Arsen>
unfortunate
<kazinsal>
generally I consider IPv6 to be an overzealous solution to a problem that wasn't relevant at the outset of the spec and still is only slightly relevant now
<kazinsal>
the overwhelming majority of service provider networks are capable of operating within IPv4
<kazinsal>
from a practical perspective, IPv4 endpoints only become a bottleneck when you have billions of simultaneous clients per /16
<kazinsal>
in practice most clients only ever have at most 16 connections active at a time and on average 3-4
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<Belxjander>
kazinsal: then I am *way* out of range for "normal" operation since I have 1 desktop, 2x RPi and have a minimum of 4 links open just for IRC... separate links for ssh to both RPi and other machines... and also other things
<kazinsal>
yeah, that's out of rnage for normal
<kazinsal>
consider the average person. they *may* have a laptop or desktop that spends most of its time in sleep
<kazinsal>
they probably have a smartphone holding a connection or two at a time
<kazinsal>
maybe they have a smart TV that's holding a connection outside their knowledge to serve ads
<Belxjander>
I'm doing all of that from AmigaOS too
<j`ey>
but 3-4 phones per house
<kazinsal>
we horrible grognards on IRC on average don't really *get* the average person's network requirements
<Belxjander>
PPC AmigaOS 4.x is a 32bit build... with 64bit extensions explicit for disk storage access at the moment
<Belxjander>
kazinsal: Android OS devices? << is that what you mean by SmartPhone ?
<Belxjander>
or iPhone apple provision kit?
<kazinsal>
android, iPhone, whatever. the over-period-of-time average comes out similarly
<Belxjander>
Android only allows for 1-4 *active* process with 16 sockets per active process continiously... or it will "sleep" the process and disconnect sockets for "sleep" apps
<Arsen>
ipv6 is fiine
<Arsen>
I like that I can shove 64 additional bits of information into each computers ip :)
<kazinsal>
iOS has a disconnect after a certain period of idle time as well, sorts out hanging connections
<Belxjander>
personally I need to replace the IP stack on AmigaOS at least for my own installation...
<kazinsal>
at the cost of being slightly annoying to us grognards using protocols that expect constant connection
<Belxjander>
but I'll deal with that after fixing up some DataTypes descriptors and the XHCI driver I'm part-way through writing
<Belxjander>
kazinsal: yeah... I can't stand being disconnected and reconnected...
<kazinsal>
arguably that's a problem with the application and the protocol it works on top of
<Belxjander>
I don't mind restricting apps to 4-16 sockets usage only... as long as request and response chaining can continue as long as possible
* Belxjander
can recall a few times tweaking Mozilla Firefox settings for that and getting seriously high-speed web page performance from just that compared to trying to slam-download a whole lot in parallel
<Belxjander>
kazinsal: not always... I've always run into that with regards bandwidth shaping and throughput limits on slower links
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<geist>
okay, so after spending the evening upgrading my ryzen 3950x machine to a 5950x it's a mixed bag, but i guess anandtech spelled it out entirely
<geist>
for things like parallel compiling, etc it's not much faster. maybe 2-5%
<geist>
for single threaded performance it's clearly a bit faster. probably 20% or so. Games benefit from it
<geist>
the multithreaded stuff not being a huge big increase is basically because the memory bandwidth hasn't increased so things like lots of parallel compiling and whatnot is largely memory bound anyway
<clever>
i assume there are performance counters to measure how many cycles your spending stalled on cache misses?
<geist>
also fascinating watching what windows 10 does when scheduling it
<geist>
since it's two CCDs of 8 cores a piece (each with 32MB of L3 cache) windows a) seems to stick with CCD0 while completely sleeping CCD1 until it gets to some threshold and then spills over to the second one
<geist>
and b) totally understands the Golden Core stuff (ie, CPPC2) and loads those first
<geist>
my guess is that whole 'load up one CCD before using the second one' is what was broken in windows 11 a bit there
<geist>
linux is still oblivious to this and just spreads things across all the cores and doesn't understand CPPC2
<junon>
geist how are you seeing how windows schedules stuff across cores and whatnot?
<geist>
junon: running Ryzen Master which has a nice real time view of what all the cores are doing
<geist>
and basically how fast they're running in real time, presumably by reporting the cycles it ran last second
<geist>
what's interesting is windows didn't seem to do this on the 3950x (zen 2)
<geist>
in general it seemed to keep the 4x4 core CCDs loaded fairly evenly, though it understood the Golden Core stuff
<geist>
so there seems to be a real behavioral switch in zen 34
<geist>
3 that is
<geist>
that sticking to one CCD really avoids L3 cache latency issues at the expense of total L3 cache utilization being lower since you're basically not using the second half of 64MB L3 a lot of the time
<geist>
it's possible windows was doing the same thing on the 3950x but since each cluster was only 4 cores it immediately spilled over and started the other ones
<geist>
https://i.imgur.com/S7Mx6KV.png is what i'm talking about re: using the first cluster of 8 before starting up the second one
<geist>
also notice the cores with the gold star and the white dot. those are the cores that CPPC2 have said are better than the others, and windows favors them
<geist>
clever: re stalls presumably so yeah. It makes sense, the new zen 3 cores are N units faster per core, but the whole thing is memory bandwidth starved when you really spool up all of them
<geist>
In a memory intensive thing that is. Also if your scheduling is moving data back and forth between the L3s you pay the penalty a lot, but then it was even worse with 3950x since there were 4 L3s instead of just 2
<clever>
i think `perf top` and `oprofile` can be configured to fire an irq and record a sample on something like every 1000th cache miss?
<geist>
So my guess is the windows 11 scheduling on these thing debacle is it temporarily forgot about the split L3 and started scheduling things across the cores willy-nilly and then suddenly the average cache latency shot up
<clever>
and then over time, that shows hot-spots of what code is causing misses
<Bitweasil>
"Golden core" is the one core that turbos best?
<geist>
Yah. Basically has more headroom than the other ones. For every CCD AMD promises a golden core and one silver core
<Bitweasil>
Oh, per chiplet? So you've got two on the higher end SKUs?
<geist>
Yah. See the two golden stars on the last screenshot
<clever>
geist: oh, and on the subject of scheduling, but in LK, if something like a uart irq gets handled on core-0, but core-1 is idle, what causes core-1 to reschedule, rather then forcing core-0 to stop its task?
<Bitweasil>
Ah, got it. Neat!
<geist>
clever: LK is extremely dumb about it right now. Basically whenever it wakes up a thread anywhere it sends a broadcast IPI to all the other cores to tell them to reschedule, and then it fights it out
<clever>
geist: ah, thats good enough, if the total count of woken threads is less then core count, but may cause some perf loss due to moving jobs to another core
<geist>
One of them will pick it up. It’s extremely inefficient but very good latency on getting a thread on a core asap
<geist>
Indeed. Doesn’t scale well beyond 4 cores or so. To do past that you need per cpu run queues and then you start to deal with balancing and latency vs efficiency things
<geist>
As are all modern ‘big’ OSes
<Bitweasil>
And then you get into NUMA stuff, and... *shudder*
<clever>
in my case, only 2 cores are at play, but i also have the option of irq balancing
<geist>
Yeah for 2 cores it works nicely, you’re basically always reevaluating the single run queue on all cpus
<clever>
that just leaves implementing IPI's then
<Bitweasil>
Or be a Raspberry Pi and just say forget it, and put mailboxes in.
<Bitweasil>
That interrupt controller on the 2 is one of the laziest pieces of work I've ever seen...
<geist>
yeah it's a super piece of shit. that's honestly the main thing that turned me off to the whole RPI thing
<clever>
Bitweasil: i suspect the IPI logic for the VPU is also mailboxes, but in a different form
<geist>
RPI4 has redeemed itself a bit
<Bitweasil>
The Rpi4 has a GIC... 400, maybe?
<geist>
yah
<clever>
but all of the PL011 uarts share a single irq on the GIC
<Bitweasil>
I've not looked at it yet, that's a later project. Can that do actual IRQ routing? On the Raspbian install I have, it doesn't seem to.
<clever>
so you still need custom logic to know which uart fired the irq
<geist>
it still has some dumb frankensteiny shit with the legacy irq controller, but you can basically disable it
<Bitweasil>
I still take all my hardware interrupts on core 0 with my Pi4.
<geist>
clever: hmm, but at least the miniuart is separate right? it has its own uart?
<geist>
er irq
<clever>
geist: yeah, but the mini-uart is basing its baud rate on the VPU clock freq
<clever>
so you have to disable the VPU power savings, or the freq will be a moving target
<geist>
that's the console uart right?
<Bitweasil>
I don't think it has an IRQ, does it? The Pi4 at least includes a ton of PL011s, so there's no good reason to use the miniUART.
<clever>
depends on pinmux
<clever>
either uart can be the console
<geist>
so wait, there are N pl011s and they all use a single irq?
<clever>
page 85, irq 57 is an OR of every PL011 uart
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<geist>
for LK sure, fine. but zircon there are two completely different classes of IRQs: stuff the kernel grabs (looks like legacy LK irq registration) and user space IRQs which go through a different path
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<geist>
would have to install some sort of pre-filter for one of the user space irq grabs that fires user space and also fires the kernel one
<geist>
since it's an OR you cant tell that more than one has triggered either, so thats even worse
<clever>
page 86, every spi interrupt goes to irq 54
<clever>
every i2c interrupt goes to 53
<clever>
and every pl011 irq goes to 57
<geist>
geezus what was their problem? the GIC 400 can handle like 1024 irqs
<clever>
i think the problem, is compatability with the legacy irq controller
<clever>
so the old legacy limit of 64 irq's still applies
<clever>
and they didnt want a seperate irq table when using the gic
<geist>
sigh. well anyway. whatever
<geist>
enough anger at raspberry pi for a day
<geist>
this thing is such a piece of shit
<Bitweasil>
Time for an ODroid N2+?
<geist>
at the same time it is the thing that everyone likes, so totally torn
<clever>
geist: could an EL3 hide this? by catching irq 57, and then emulating 8 diff interrupts?
<geist>
and i was just trying to get folks at work interested in a zircon port
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<Bitweasil>
*ew*.
<geist>
this sort of shared irq between user and kernel is exactly the thing that i dont think has a good solution
<Bitweasil>
That would mean you need to control the bootloader too, potentially, to run zircon.
<geist>
yep
<clever>
Bitweasil: or EL2 instead
<geist>
EL2 wouldn't help. you'd have to route that irq as a secure one
<geist>
to have it trapped in another EL. thus EL3 it has to be
<clever>
hypervisor cant trap interrupts?
<geist>
it can trap *all* interrupts
<geist>
not selectively
<clever>
ahhh
<clever>
so EL2 would have to intercept everything, then tell the GIC to fake a virtual irq and go back to EL1
<geist>
to selectively trap you have to map one to FIQ basically (ie, secure IRQ) and then per EL it can trap IRQs or FIQs or both
<Bitweasil>
Yeah, you can flag stuff as "secure" or "not secure," though... the legacy interrupt controller doesn't really support that either.
<geist>
hence how FIQs got recycled to mean 'secure IRQ'
<clever>
yeah, i see
<Bitweasil>
I thought the GIC could route certain interrupts down to secure, without having to use FIQ?
<Bitweasil>
But it's been a year+ since I looked at the GIC stuff.
<geist>
i dont thin so? I think you just end up putting them in group 0 which you then map to FIQ
<Bitweasil>
Hm, that might be the mechanism.
<geist>
i was hoping arm would clean all of that up in armv9 with some new GIC v5 or something but i dont think theres any fundamental difference there
<Bitweasil>
ARM A series interrupts are a bit dumb, I don't know why only the M series gets a competent interrupt vector table.
<Bitweasil>
I thought 9 was more or less just saying, "Yeah, look, please put all these 8.x extensions in and call it 9" for the most part.
<clever>
and page 87 of the pdf i linked shows the mapping from legacy interrupts to gic interrupts
<geist>
i'd love there to be something basically in the GIC that says 'which EL do you want this to route to?' and then expand the IRQ signalling wires to the core that let something external trigger + what EL/secure it wants to be
<geist>
Bitweasil: that's my read from it too. armv9 is effectively armv8.5 + SVE as a baseline
<Bitweasil>
*nods*
<geist>
i think it's so much that that stuff that's considered 8.6 is 9.1, 8.7 is 9.2, etc
<geist>
i remember seeing a slide to that effect a while back
<Bitweasil>
I guess SVE is "new," but... that's still kind of off in the coprocessor space, the core is still ARMv8 plus a bunch of 8.x extensions.
<geist>
yah except v9 mandates SVE as being a baseline
<josuah>
I think Nordic, in its ARM Cortex-M, uses the "real" interupt table for its bootloader/wireless driver, letting another "software" interrupt table for the user
<geist>
so by saying its v9 it draws a new line
<Bitweasil>
Right.
<Bitweasil>
Hey, anyone want a Chromecast Ultra, and a non-standard PSU for it so it won't run at 4k?
<Bitweasil>
I've got one laying around unused.
<geist>
heh i'm swimmig in extra chromecasts too
<geist>
though the plain old ones. as new stuff gets chromecast built in i've neede it less and less
<Bitweasil>
I was hoping the wifi on it was better than the... oh, 2 or so I've got, but I gave up and went wired instead.
<geist>
yah i use wired on my ccast ultra too
<Bitweasil>
And I don't need 4k.
<geist>
but but stadia pro!
<Bitweasil>
I've got the Ultra, but without the wired ethernet/power adapter.
<geist>
everyone plays stadia
<Bitweasil>
What's Stadia?
<clever>
Bitweasil: running games in the cloud, and streaming it back to you
<Bitweasil>
Oh, right, the thing have neither the bandwidth nor the latency for. :D
<geist>
heh
<geist>
honestly the stadia stuff works surprisingly well, i just dont know what niche its trying to solve
<geist>
though it's not like google made that up, there are competitors in that market