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<
_florent_ >
josuah: This is also exposing an AXI-Lite or Wishbone Bus
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<
_florent_ >
with an example of re-integration for both generated as verilog :https://github.com/enjoy-digital/litex_rp2040_pmod_test/blob/master/icebreaker.py#L59-L143 or direct use of the LiteX flow.
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