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<_florent_>
josuah: yes sure, if you want. I should also open an issue to share more about this.
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<MoeIcenowy>
_florent_: BTW 8192 L2 size seems to be too big for Tang Primer 20K
<MoeIcenowy>
the FPGA seems to be quite lack of BRAM (called BSRAM by Gowin)
<MoeIcenowy>
BTW what's the point of moving self.rst from PLL reset to cd_sys reset?
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<_florent_>
MoeIcenowy: I indeed reduced L
<_florent_>
L2 cache size in Linux-on-LiteX-Vexriscv
<_florent_>
For the reset, the PLL reset is apparently not working correctly, with the previous code, issuing a reset from the BIOS was freezing the SoC
<_florent_>
this will need to be investigated, for now I did this change to avoid it
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