_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<somlo> and was wondering, in re. Rocket (and the fact that its RAM starts at 0x8000_0000) what I'm missing (since it seems to work) :)
<somlo> what do you mean by the comment that the dma region "covers lower 4GB only" ?
<somlo> thinking mainly about issue #1753, and whether this has anything to do with Rocket DMA being broken when using LiteX AXIUpConverter, but working when rocket does its internal LiteDRAM width matching
<somlo> LMK if this is better done over email (or as part of #1753 itself) :D
<somlo> sorry, noticed my cut'n'paste screwup earlier, the line I'm talking about is: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1141
<_florent_> somlo: Hi, I was doing these change for NaxRiscv, but the # FIXME was already there. The change I did change a little bit the behavior for Rocket, since now the interconnect will be in 64-bit (the width of the DMA bus) and SDCard/SATA modules connecting to it will be converted to 64-bit. (Before the interconnect was 32-bit and there was a converter to the DMA bus in 64-bit).
<_florent_> I'll have a closer look at the FIXME, to see if that's still relevant
<somlo> right, I noticed it was there before too, and dma with rocket also worked before (issue #1753 was filed before this change :)
<somlo> I'm still building the post-change bitstream but assume it will be the same as before (dma works at least when rocket does its own litedram width matching)
<somlo> but the change made me notice the fixme, and wonder what it actually means :)
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<josuah> 0x80000000 is less than 4GB?
<josuah> 4GB limitation sounds a lot like only supporting 32-bit of address space
<josuah> but maybe I misunderstood your question.
<somlo> joshuah: thanks, that makes sense -- I got a bit confuzzled in my binary/hex arithmetic :D
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