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<qschulz>
warpme: I clicked on the link you provided, no 403 and I wasn't logged in with a GitLab account
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<Kwiboo>
warpme: yes, I will try to update my combined u-boot branch at github at some point in near future, pushed to u-boot gitlab to ensure the rk3528 changes passed CI
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<warpme>
qll. many thx! Btw: some time in past i was trying to get hdmi support on 3528. I recall i got sort of working dw-hdmi (at least in dmesg looked all ok). I was blocked by no vop3 support. Any Yan give me some hints how to reuse 3576 vop2 additions to add minimal vop3 required by 3528. My knowledge is to weak to get reasonable probability i get it working. Have you plans to look on 3528 hdmi or rather we need to wait till Andy
<warpme>
provides minimal vop3 support?
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<Kwiboo>
warpme: I have no immediate plan to work on vop support, maybe in future, at the moment my interest is to get improved support in Linux so we can use DTs from dts/upstream in U-Boot ;-)
<warpme>
ah ok. thx for info!
<Kwiboo>
CounterPillow: did you manage to get gpu freq to work on rk3576? if I understand correctly tf-a will mostly configure the gpu to use pvtpll and not a normal pll, instead ft-a set a ring length depending on requested freq and the voltage in opp affect how fast gpu will run
<CounterPillow>
It appears to work with the fixed scmi clk IDs, yes. I no longer get panfrost job timeouts and glmark runs at an acceptable framerate
<CounterPillow>
I didn't look in detail into whether the GPU is at the fastest speed it can be, just that it no longer is stuck at the lowest
<Kwiboo>
cool, looked like the tk3576 use the cru CLK_GPU as core clock so was wondering if it has any affect, maybe because the scmi clock is set to ~200MHz tf-a disable use of pvtpll and the CLK_GPU is one really used
<CounterPillow>
do we not have any OPPs for the GPU or something?
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<Kwiboo>
and when pvtpll is enabled the rate or CLK_GPU does not matter
<CounterPillow>
can I check whether pvtpll is enabled from within linux?
<Kwiboo>
I am also not sure that all rates can be achieved with current int plls, i.e. 1188 MHz with div=2 -> 594 MHz
<Kwiboo>
for rk3528 I use the scmi clock as the gpu core clock, and I am wondering if rk3588 and rk3576 should really be using something like that to work as intended, or at least to be able to reach top performance
<Kwiboo>
I do not think the pvtpll regs is in normal device mem and not in secure mem, so should probably be possible to check from Linux
<CounterPillow>
Possibly, I've done zero investigations into performance atm because I'm still at the stage where random things are just straight up broken like eMMC :|
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<Kwiboo>
BIT(8) of CRU_CLKSEL_CON(165) seem to determin if pvtpll is used for gpu or normal pll, if I understand the tf-a code correctly
<CounterPillow>
tl;dr: if PD_NVM is turned off and then turned back on again, it never comes up the same, and writes to sdhci control registers lock up the SoC
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<Kwiboo>
CounterPillow: ahh, thanks for clarification on the emmc issue :)
<CounterPillow>
afaik sre was in the process of asking Rockchip whether that's caused by BIU (linked clocks), but I haven't heard back yet. Linked in the issue is an interesting downstream hack that just forces the PD on in the mmc host driver (a bit sus if you ask me)
<qschulz>
Don't know if related, but IIRC there were issues for the card detect pin when using the card detect function instead of cd-gpios on rk3588 because of some power domain thingy
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<CounterPillow>
I know the register range it locks up on when accessing, it's the CQHCI regs within the IP itself.
<CounterPillow>
my best guess (though my guesses are usually terrible) right now is that someone did an oopsie and is auto-gating a clock on PD shutdown but forgot to also auto-ungate it on PD re-power, but its initial power-on-reset state is enabled
<CounterPillow>
if someone is interested in testing that theory, you could probably dump all the clock registers (including the ones in GRF) in u-boot, then disable the PD, then re-enable the PD, then dump them again, and then run the two snippets through diff -u
<CounterPillow>
though if it's a secure clock I think we can't dump that
<qschulz>
secure clock should be dumpable only from OP-TEE/TF-A when in EL3 I believe?
<qschulz>
It wouldn't make sense otherwise
<CounterPillow>
hmmm, maybe I should just use tf-a for this exercise then
<robmur01>
qschulz: the "thingy" being a question of how a powered-off MMC controller can raise its own interrupt to say it needs powering back on ;)
<qschulz>
robmur01: details :)
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<CounterPillow>
robmur01: I was wondering why my Reviewed-by/Tested-by e-mail had you lacking from the "To:", apparently however the mailing list delivered it to me made KMail both not have you as a recipient other than the Cc and it messed up the Subject as well :/
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