ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<mort>
Hey, what's the proper way to expose a potmeter? I have a device where it's currently exposed as the keys f1-f6 on an input device, but that doesn't feel very appropriate
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<broonie>
mort: Feels like it might be IIO?
<mort>
as in industrial I/O?
<broonie>
Yes.
<mort>
I'll check it out
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<broonie>
arnd: Are you going to submit/merge that firmware patch?
<ajb-linaro>
but I'm confused at how many total IRQs the GIC has in this case - or the SGI vs PPI vs SPI IRQs
<geertu>
ajb-linaro: You cannot find out asily without looking at the datasheet of the SoC.
<geertu>
The DT can only tell you the largest GIC_SPI number used
<ajb-linaro>
this perhaps explains why the original author skipped the wiring up of IRQs in their version of the model
<ajb-linaro>
geertu: thats what I need, internally QEMU models them as
<ajb-linaro>
* [0..N-1] SPIs
<ajb-linaro>
* [N..N+31] PPIs for CPU 0
<ajb-linaro>
* [N+32..N+63] PPIs for CPU 1
<ajb-linaro>
so I need to know what N is ;-)
<geertu>
16 SGIs?
<geertu>
16 PPIs?
<geertu>
I thought SPIs always start at 32
<geertu>
You can easily have +400 SPIs
<ajb-linaro>
the diagram in the BCM2711 has SPI ID's from 32 to 216 - so I guess 216?
<geertu>
So that's GIC_SPI 0..184 in DTS
<ajb-linaro>
geertu: how did you arrive at the 184 from the dts?
* ajb-linaro
guesses at
<ajb-linaro>
* - SPIs 32 - 216 (184 total)
<ajb-linaro>
* - PPIs 32 * BCM283X_NCPUS (128)
<ajb-linaro>
* - SGIs 16? * BCM283X_NCPUS (64)
<ajb-linaro>
not sure if the number of SGIs is fixed - the GIC-400 says "Each CPU interface can generate a maximum of 16 SGIs, ID0-ID15" which implies is
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<apritzel>
Each GICv2 has 16 SGIs and 16 PPIs per core, plus up to 988 SPIs. The interrupt ID arranges them as SGIs: 0-15, PPIs: 16-31, SPI: 32-1019
<apritzel>
how many SPIs is set at integration time, as can be read from GICD_TYPER[4:0]
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<geertu>
ajb-linaro: offset 32
<apritzel>
ajb-linaro: if I can trust my 5-minute /dev/mem hack, then the RPi4 GIC implements 224 SPIs
<apritzel>
TYPER is 0x0000fc67
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<ajb-linaro>
apritzel: hmm odd so the PPI ID I see start at 26 - so is that just some sort of weird offset numbers (PPI IDs being 16-32?)
<apritzel>
yes, the PPIs are mapped to the GIC interrupt IDs 16-32
<apritzel>
in the DT we use "relative" numbers, the first cell tells you which (SPI, PPI)
<apritzel>
so <GIC_PPI 9 ...> means PPI #9, which is GIC interrupt ID 25
<apritzel>
similarly <GIC_SPI 2 ...> means SPI #2, so interrupt ID 34
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<apritzel>
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml is the authority here
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<ukleinek>
broonie: I think this check for if (IS_ENABLED(CONFIG_SPI_DYNAMIC) && !device_is_registered(&ctlr->dev)) in __spi_add_device is broken in several ways
<ukleinek>
a) even without CONFIG_SPI_DYNAMIC the controller might go away
<ukleinek>
b) what happens if the controller goes away just after the check?
<ukleinek>
oh, b) is not an issue, spi_unregister_controller takes the same lock
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<broonie>
ukleinek: controller going away is probably an issue though.
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