whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
lf has quit [Ping timeout: 250 seconds]
lf has joined #amaranth-lang
<_whitenotifier-e> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/nextpnr/compare/1f7af943c8ad...e85cf1f3cd4c
<_whitenotifier-e> [YoWASP/nextpnr] whitequark e85cf1f - Update dependencies.
emeb_mac has joined #amaranth-lang
Guest8599 has joined #amaranth-lang
Guest8599 has quit [Client Quit]
bl0x_ has quit [Ping timeout: 250 seconds]
bl0x_ has joined #amaranth-lang
Vonter has joined #amaranth-lang
Degi_ has joined #amaranth-lang
Degi has quit [Ping timeout: 240 seconds]
Degi_ is now known as Degi
Xesxen has joined #amaranth-lang
<d1b2> <TheManiacalLemon> l
<d1b2> <TheManiacalLemon> Whoops. Actual question:
<d1b2> <TheManiacalLemon> If I'm trying to generate verilog via the amaranth.cli module, is there an attribute I can put on my top-level Elaboratable that causes those signals to get passed through to the verilog input/output list? I tried using self.ports but that didn't seem to help, my top module only has clk and rst on it.
<d1b2> <TheManiacalLemon> Ahhh, hold on. I think the issue is I needed to change the following line in my main:
<d1b2> <TheManiacalLemon> main(dut) to main(dut, ports=dut.ports)
emeb_mac has quit [Quit: Leaving.]
bvernoux has joined #amaranth-lang
Vonter has quit [Quit: WeeChat 3.4]
emeb_mac has joined #amaranth-lang
GenTooMan has quit [Ping timeout: 240 seconds]
Bluefoxicy has quit [Ping timeout: 256 seconds]
Bluefoxicy has joined #amaranth-lang