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<TheManiacalLemon> Whoops. Actual question:
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<TheManiacalLemon> If I'm trying to generate verilog via the amaranth.cli module, is there an attribute I can put on my top-level Elaboratable that causes those signals to get passed through to the verilog input/output list? I tried using self.ports but that didn't seem to help, my top module only has clk and rst on it.
<d1b2>
<TheManiacalLemon> Ahhh, hold on. I think the issue is I needed to change the following line in my main:
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<TheManiacalLemon> main(dut) to main(dut, ports=dut.ports)