15:16 <_whitenotifier-e> [amaranth-boards] DaveBerkeley opened pull request #196: Added platform file for ColorLight i9 - https://github.com/amaranth-lang/amaranth-boards/pull/196

18:07 <Sarayan> style question: should local sync of comb signals part of self? If yes, what is the naming convention?

18:07 <Sarayan> sync or comb

18:54 <d1b2> <garbile> Where can I find an example of using the built-in iCEBreaker UART? https://github.com/amaranth-lang/amaranth-boards/blob/main/amaranth_boards/icebreaker.py#L27

18:55 <d1b2> <garbile> I don't need high-speed like TNT's Verilog code. Simplicity is more important

19:01 <adamgreig[m]> garbile: maybe something like https://github.com/amaranth-lang/amaranth/blob/main/examples/basic/uart.py ?

19:03 <d1b2> <garbile> That doesn't seem to use the platform resource, though. There's already a UART on the board that's used to program it, and I wanna use that

19:07 <vup> Sarayan: I only make signals that need to be part of self (ie ports) part of self.

19:08 <adamgreig[m]> garbile: the platform resource just says "these two fpga pins are called uart tx and uart rx", and on the PCB, they're wired to the FTDI chip that sends them over USB

19:08 <adamgreig[m]> there's no UART built in to the FPGA itself; if you instantiate that UART from the amaranth examples folder, you can connect its pins to the uart.tx and uart.rx from your platform

19:10 <adamgreig[m]> something like: uart = m.submodules.uart = UART(divisor=12); uart_pins = platform.request("uart"), m.d.comb += uart_pins.tx.o.eq(uart.tx_o), uart.rx_i.eq(uart_pins.rx.i)

19:11 <d1b2> <garbile> And then I can just connect to /dev/USB0?

19:11 <adamgreig[m]> yea

19:12 <d1b2> <garbile> Awesome, I'll try that

19:13 <Sarayan> vup: does it have an impact on port naming in cxxrtl?

19:15 <vup> port naming?

19:23 <Sarayan> yeah, when you reach into the class to look at the state

19:25 <Sarayan> I know amaranth does some magic to get the signal names used in python, dunno if that reaches local variable names

19:26 <vup> it does

19:28 <vup> but not sure you can count internal signals as ports :) anways, you prbabl

19:28 <vup> probably needy the higher debug levels to not loose some of them

19:57 <cr1901> garbile: https://github.com/icebreaker-fpga/icebreaker-amaranth-examples/tree/master/icebreaker/uart

19:59 <d1b2> <garbile> @cr1901 That's awesome, thank you!