<lsneff>
I found a paper from a few years ago that shows how it's possible to overload python's control flow constructs. I implemented a POC (https://gist.github.com/lachlansneff/49c463b536859496c84f3d7af326a8eb). If expanded upon, this would provide a way to use `if` and `match` instead of `with m.If(...)` and `with m.Switch(...)`.
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<tpw_rules>
at that point you're just using myhdl
<lsneff>
I’ve never used myhdl; I assume it had some significant shortcomings?
<lsneff>
Oh wow, so it’s literally verilog but python
<cr1901>
I don't claim to understand the rationale, but compared to migen, context managers for control flow were one thing explicitly added. I doubt wq would want to remove them even putting aside how it's a breaking change
<tpw_rules>
i remember when i first learned amaranth i proposed a similar patch to use python's native syntax more closely
<tpw_rules>
but then i realized that a) there's myhdl if you want it and b) i think the context manager and having separate syntax approach is kind of ugly, but useful and clear
<tpw_rules>
it's obvious what is and isn't hdl, and makes you more naturally think of more powerful things
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<tpw_rules>
idk, maybe interlacing amaranth and python control structures is cursed
<tpw_rules>
but it's probably more cursed in myhdl
<d1b2>
<dragonmux> our take is that the context manager approach makes sense to clearly delineate the DSL so there are no restrictions on Python control flow and therefore no restrictions on the generative/meta-programming aspect of Amaranth that so dearly benefits it
<_whitenotifier>
[amaranth-lang/amaranth-lang.github.io] whitequark 9e836de - Deploying to main from @ amaranth-lang/amaranth@1f1d1894413f6aca3ea8792f5e5f87ce3a070191 🚀
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<Sarayan>
lsneff: one other aspect of leaving native python as-is is that you can write code generators inline without wondering if there's going to be bad interactions
<d1b2>
<dave berkeley> I was just looking at streams. I have a Litex SoC that I want to integrate my amaranth code into, plus some legacy VHDL. So, for now, I probably want to talk to my new SPI device via a Litex stream. I look forward to the day when I can work entirely in Amaranth. Is there a roadmap for the migration? Also : CXXRTL was invaluable for understanding the legacy VHDL. These tools are excellent.
<lsneff>
All that makes sense. In this case, it doesn’t just assume all control flow is something that would happen on the fpga, so you don’t get weird restrictions, but it true that it wouldn’t be as clear anymore
<Degi>
For example with match case you can't generate the cases with a for loop
<Degi>
At least python gives me a syntax error when I do match 3: for i in range(4):
<lsneff>
Oh good point
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<key2>
miek: with some more sniffing, I can tell you that the modification you made can sometimes (very rarely) discard en entire packet (in my case of 512 bytes). Any hint ?