01:02 <_whitenotifier-e> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/f8b58b705730...4c184284ad4f

01:02 <_whitenotifier-e> [YoWASP/yosys] whitequark 4c18428 - Update dependencies.

02:30 <d1b2> <4o> it's been a while since i used the tool, and looks like i forgot something basic https://paste.debian.net/1229976/ why does it complain on elaborate interace?

02:46 <adamgreig[m]> 4o: you're passing the class `wrap` into SImulator which takes an instance of an Elaboratable

02:46 <adamgreig[m]> it might make it clearer to name class types with a camelcase name like Wrap and keep all-lowercase names for instances, `wrap = Wrap()`, then you can pass `wrap` into `Simulator(wrap)`

02:47 <adamgreig[m]> (also it's conventional to create the Module inside elaborate and therefore not need to bind it to self, but that's not related to your problem)

02:47 <d1b2> <4o> so the right thing to do is Simulator(wrap()), right?

02:48 <d1b2> <4o> aka pass instance, not the class

02:48 <adamgreig[m]> I think the "right" thing to do is name the class Wrap and then `Simulator(Wrap())` but sure

02:48 <adamgreig[m]> yea, you have to pass an instance

02:48 <adamgreig[m]> it's quite a bizarre error

02:48 <d1b2> <4o> thx for help

02:49 <adamgreig[m]> also, your test bench method shouldn't take any arguments (so just plain `bar()`)

02:50 <adamgreig[m]> let it capture the uut as a closure (so you _will_ need to bind `wrap = Wrap(); s = Simulator(wrap); def bar(): yield wrap.i.eq(1)`)

02:51 <adamgreig[m]> and in your test you probably need some bare `yield` statements to drive any clock cycles, or you'll just print the initial value of `o`, since it's a synchronous assignment and you haven't run the sim for any time

02:51 <adamgreig[m]> but that means you'll also probably want s.add_sync_process(bar) and s.add_clock(1/10e6) etc

02:52 <adamgreig[m]> if it's helpful, here's a complete little example of a module and simulator, set up to run with `pytest counter.py`: https://github.com/adamgreig/amaranth-examples/blob/master/amaranth_examples/counter.py

02:54 <vup> I just read s.add_sync_process(bar) as s.add_sync_progressbar(), which would be pretty neat aswell^^

07:16 <SimonSapin> agg: that makes a lot of sense, thanks!

09:27 <d1b2> <dave berkeley> I'm trying to use a Memory() where the writes to write_port() are in one class and the reads from read_port() in another class. Just a single clock domain. I'm getting the warning "DriverConflict: Memory 'mem' is accessed from multiple fragments, hierarchy will be flattened" but I'm not sure why. What should I look for?

10:29 <whitequark> this warning is emitted because you have write_port() and read_port() added to different modules

10:31 <d1b2> <dave berkeley> So if I want to write from a different module, I should have the calls to write_port() and read_port() in just one module, but can then access it from another? I'll experiment, thanks.

10:33 <whitequark> yeah

10:36 <d1b2> <dave berkeley> The warning has gone. Thanks.

11:56 <_whitenotifier-e> [amaranth-lang/amaranth-boards] whitequark pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth-boards/compare/aaf18252e457...d3fb7331b2b1

11:56 <_whitenotifier-e> [amaranth-lang/amaranth-boards] whitequark d3fb733 - genesys2: don't pass strings as resource numbers.