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<4o> it's been a while since i used the tool, and looks like i forgot something basic https://paste.debian.net/1229976/ why does it complain on elaborate interace?
4o: you're passing the class `wrap` into SImulator which takes an instance of an Elaboratable
it might make it clearer to name class types with a camelcase name like Wrap and keep all-lowercase names for instances, `wrap = Wrap()`, then you can pass `wrap` into `Simulator(wrap)`
(also it's conventional to create the Module inside elaborate and therefore not need to bind it to self, but that's not related to your problem)
<4o> so the right thing to do is Simulator(wrap()), right?
<4o> aka pass instance, not the class
I think the "right" thing to do is name the class Wrap and then `Simulator(Wrap())` but sure
yea, you have to pass an instance
it's quite a bizarre error
<4o> thx for help
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also, your test bench method shouldn't take any arguments (so just plain `bar()`)
let it capture the uut as a closure (so you _will_ need to bind `wrap = Wrap(); s = Simulator(wrap); def bar(): yield wrap.i.eq(1)`)
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and in your test you probably need some bare `yield` statements to drive any clock cycles, or you'll just print the initial value of `o`, since it's a synchronous assignment and you haven't run the sim for any time
but that means you'll also probably want s.add_sync_process(bar) and s.add_clock(1/10e6) etc
I just read s.add_sync_process(bar) as s.add_sync_progressbar(), which would be pretty neat aswell^^
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agg: that makes a lot of sense, thanks!
<dave berkeley> I'm trying to use a Memory() where the writes to write_port() are in one class and the reads from read_port() in another class. Just a single clock domain. I'm getting the warning "DriverConflict: Memory 'mem' is accessed from multiple fragments, hierarchy will be flattened" but I'm not sure why. What should I look for?
this warning is emitted because you have write_port() and read_port() added to different modules
<dave berkeley> So if I want to write from a different module, I should have the calls to write_port() and read_port() in just one module, but can then access it from another? I'll experiment, thanks.
<dave berkeley> The warning has gone. Thanks.