<marble> is there a way to access a signals value from previous clock cycles during formal verification without instantiating a register for that?
<marble> Ah, Past...
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I'll have more to announce at a more reasonable time, but... I used Amaranth in the past few days to revive a dead ISA card I had.
It was fast enough to prototype a design for icebreaker- kinda like a scripting language- to dump a PAL and work as a TTL chip tester, to find the bad chip :D
<widlarizer> I want to test my CPU with various programs loaded into Memory. However, to write into Memory, I have to initialize it, which seems to only be possible in elaborate, so I have to build the design multiple times. This seems to not work, probably because my m instance of Module isn't in top scope: https://www.toptal.com/developers/hastebin/yojiqekibe.py
slightly light on very dark? Is the aim being totally unreadable?