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[amaranth] cestrauss closed issue #568: cxxsim: error when reading unused combinatorial signal - https://git.io/Jycex
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<Peanut>
How does one describe an open drain signal? In Verilog, I've used "assign gpio_a0 = sck ? 1'bz: 1'b0;"
<d1b2>
<dragonmux> The easiest way is to describe it in terms of an output with enable (or io if you need the input half too) - set the .o part of the signal to the on state (0 for open drain usually), and then toggle the signal with the .oe component
<d1b2>
<dragonmux> when .oe is 0, the signal will be high-Z pulled however the physical pin is pulled, and when .oe is 1 the signal will be driven per the state of the .o signal
<Sarayan>
Peanut: open-drain does not exist in (modern) fpgas and not much in asics either, so amaranth doesn't support it as-is
<Sarayan>
tristate/pull/etc doesn't exist in fact, it's all driven all the time
<Peanut>
ECP5 in this case - I guess I2C is a bit old-fashioned by now indeed.
<Sarayan>
it exists in *external* busses, but not on-die
<Sarayan>
i2c is external
<Peanut>
Yes, I'm only using it on the external pins, not inside.
<Sarayan>
ahhhhhh ok
<Sarayan>
then I concur with dragonmux, set the output to 0 and use output-enable to toggle
<Peanut>
dragonmux: How does one 'describe it in terms of an output enable' ?
<Peanut>
Or can I just do "m.d.comb += i2c.scl.o.eq(0), i2c.scl.oe.eq(self.i2c_scl)" ?
<Sarayan>
you have to invert oe though
<Sarayan>
oe=1 => connect pin to 0
<Sarayan>
oe=0 => tristate (or pullup depending on your pin config)
<Peanut>
Ah, of course, thanks - that was the error I was about to make.
<Sarayan>
you'll note that the solution rejoins what I was saying, o and oe are always driven, there's no Z anywhere
<Peanut>
*nods* well, it compiles.. just have to get the clocking right, and I should be able to test it on hardware, almost done.
<d1b2>
<dragonmux> it'll have synthesised better, most likely, than trying to describe in terms of 'z' as Yosys doesn't really support 'z' and has to do tricks to make it synthesisable
<Peanut>
dragonmux: Yosys did warn about my 1'bz in Verilog, but it worked just fine.
<d1b2>
<dragonmux> this circles back to Sarayan's point that 'z' doesn't exist in any modern FPGAs
<d1b2>
<dragonmux> if you're wondering btw.. Amaranth gets around this by explicitly instantiating the device IO primitive directly so it never has to deal with 'z', only pure driven signals and the pad 'inout' signal
<d1b2>
<286Tech> Hmm, my Amaranth CPU keeps getting optimized away by Yosys and I cannot figure out why by looking at the synthesis log. It removes a bunch of things but it's not clear what exactly gets removed.
<Peanut>
*pulls out hair* something messed up my indentation...
<d1b2>
<dragonmux> does the CPU drive anything that's an output on the device? (either by being a peripheral with an output, or by bonding internal CPU signals to pins)
<d1b2>
<dragonmux> (if the answer's no, then it's being optimised out as yosys thinks it's not doing anything as it produces no outputs)
<d1b2>
<286Tech> @dragonmux I have created a third read port on my register file and I'm routing that to the 8 LEDs on my board.
<d1b2>
<286Tech> And I know that that worked because I did the same thing in the previous version of my CPU.
<d1b2>
<dragonmux> not sure what to tell you then.. only thing we can think of is sticking a keep attribute on something like the program counter
<d1b2>
<286Tech> The yosys log doesn't help much either, it just reports that it removes almost everything. I'm sure I'm missing like a single signal that I haven't assigned or something, but I cannot find which one.
<d1b2>
<TiltMeSenpai> lol... map the program counter and a couple other important bits to random pins?
<d1b2>
<TiltMeSenpai> "random" meaning known safe but irrelevant pins
<d1b2>
<286Tech> Ok, let me try that
<d1b2>
<TiltMeSenpai> it could slow down your fmax a bit, but it's better than your cpu getting deleted
<d1b2>
<286Tech> Ok, now I finally have several LUTs that are used. Far too little of course, but at least it doesn't optimize everything away.
<d1b2>
<286Tech> I also see a lot of: Creating register for signal \DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$169_EN' using process \DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$201'. created direct connection (no actual register cell created).
<d1b2>
<286Tech> I have been staring at this for too long. Time for some dinner 😄
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<Peanut>
I've got a working I2C block. Same functionality as the Verilog one, but only uses 56 instead of 81 slices (out of 12144...)
<Peanut>
Eeks, typo: 67 instead of 81 (out of 12144)
<Peanut>
Does anyone know what a GSR is (as part of the Trellis Device Utilisation Report) ?
<tiltmesenpai[m]>
I wanna say Global Set/Reset or something? It's part of the reset/initialization sequence
<Peanut>
Brought the usage down to 55/12144 slices (0.45%).
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<Sarayan>
286Tech: stuck clock maybe?
<d1b2>
<286Tech> Hmm, I don't think so. I only have one clock source and I can drive the LEDs with a simple counter.
<Sarayan>
286Tech: I mean from yosys' POV of course
<d1b2>
<286Tech> How can I see that in the log? Is there something specific that mentions it?
<Sarayan>
no idea, honestly
<d1b2>
<286Tech> OMG
<d1b2>
<286Tech> I found it...
<d1b2>
<286Tech> I just said that I can drive the LEDs with a simple counter right? So I implemented it after I said it, and the LEDs stayed off...
<d1b2>
<286Tech> That was the hint I needed.
<d1b2>
<286Tech> For simulation I have added a clock domain called "sync" so that I could reset the core in simulation.
<d1b2>
<286Tech> Apparently the clock signal is not routed to the "sync" domain if I define it myself (since the default clock domain is also called sync).