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<d1b2>
<esden> Is there a way to stack connectors? The icebreaker-bitsy has a breakout board for the edge connector to pmod connectors. Is there an elegant way to represent that in the platform?
<_whitenotifier-e>
[amaranth] whitequark closed pull request #659: Fix 'ports' argument getting lost as it's no longer 'kwargs' - https://git.io/JDBsc
<_whitenotifier-e>
[amaranth-lang/amaranth] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±26] https://git.io/JD0CW
<_whitenotifier-e>
[amaranth-lang/amaranth] whitequark 76bb6fe - Deploying to gh-pages from @ 847e46927bb4e5e9bc56d0885535c9ff7f79f248 🚀
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<_whitenotifier-e>
[amaranth] whitequark commented on issue #660: Guidance on naming - when to say "Amaranth HDL" versus just "Amaranth". - https://git.io/JD0BU
<_whitenotifier-e>
[amaranth] whitequark commented on pull request #659: Fix 'ports' argument getting lost as it's no longer 'kwargs' - https://git.io/JD00T
<d1b2>
<286Tech> Hmm, I have renamed everything in my nmigen CPU to amaranth, but I get an error when I want to use the ulx3s from amaranth_boards: "TypeError: Resource number must be an integer, not adc". It refers to the SPIResource on line 76.
<whitequark>
oh, that's a bug in the boards repo that was hidden until recently
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<d1b2>
<286Tech> Ah ok. Is it reporterd or would you want me to make a bug report?
<_whitenotifier-e>
[amaranth-lang/amaranth-boards] whitequark pushed 1 commit to main [+0/-0/±1] https://git.io/JD0P7
<_whitenotifier-e>
[amaranth] modwizcode commented on issue #660: Guidance on naming - when to say "Amaranth HDL" versus just "Amaranth". - https://git.io/JD0jU
<_whitenotifier-e>
[amaranth] modwizcode commented on issue #661: Order of bits within pattern syntax should be documented - https://git.io/JD0jE
<d1b2>
<286Tech> Hmm, yosys segfaults when executing the MEMORY_BRAM pass. Is it possible to use the builtin yosys version of amaranth?
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<lofty>
286Tech: that's a bug; I can investigate if you want?
<lofty>
The builtin Yosys version is pretty hollowed out; mostly existing just to turn RTLIL into Verilog
<d1b2>
<286Tech> Sure, but I don't have a small example that triggers the problem.
<d1b2>
<286Tech> Unless you want to clone my CPU repo 😄
<_whitenotifier-e>
[amaranth] Ravenslofty commented on issue #661: Order of bits within pattern syntax should be documented - https://git.io/JDEUh
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<lofty>
286Tech: Yosys has the bugpoint pass to produce that "small example" :P
<d1b2>
<286Tech> How do I run that? bugpoint -command "synth_ecp5 -top top" produces an .il file with just "autoidx1" in it.
<d1b2>
<286Tech> Oh wait, maybe I could simply share the top.il file?
<d1b2>
<Lofty> bugpoint's running. Needed a somewhat ad-hoc script to make it only consider segfaults as crashes, but it works
<_whitenotifier-e>
[amaranth] martinling commented on issue #660: Guidance on naming - when to say "Amaranth HDL" versus just "Amaranth". - https://git.io/JDEm5
<d1b2>
<Lofty> I think bugpoint might be somewhat stuck in a loop
<d1b2>
<Lofty> @286Tech can you confirm this crashes on your end?