<_whitenotifier-8>
[amaranth] whitequark commented on issue #669: cxxsim: error: ‘p_sub_2e_s’ was not declared in this scope - https://git.io/JyYEU
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<_whitenotifier-8>
[amaranth] cestrauss commented on issue #669: cxxsim: error: ‘p_sub_2e_s’ was not declared in this scope - https://git.io/Jys1m
<_whitenotifier-8>
[amaranth] cestrauss closed issue #669: cxxsim: error: ‘p_sub_2e_s’ was not declared in this scope - https://git.io/JyeUa
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<Peanut>
Howdy, merry christmas. Got a Butterstick FPGA board today, so I'd like to learn about nMigen.
<whitequark>
hi!
<whitequark>
the project has been renamed to Amaranth
<Peanut>
I noticed, that's definitely news to me. First time I've heard from it is when I tried joining the #nMigen channel, and ended up in here - going through the docs now.
<Peanut>
Is there any place to read up on the history of the project/fork ?
<Peanut>
My goals are to learn how to build an I2C interface in Amaranth, and integrate it with a Risc-V core. And then get the SERDES/DCU on an ECP5 to work with this.
<whitequark>
there isn't much history to it, really
<whitequark>
the new name suits the independent community project a lot better
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<Peanut>
How does one install 'amaranth-boards' ? pip3 install --user --upgrade amaranth-boards installs something, but Python is unhappy and says 'No module named amaranth_boards'.
<Peanut>
Oh, shiny, Kicad 6.0 released today.
<whitequark>
boards aren't released on PyPI, yet
<whitequark>
you can install the git version though
<Peanut>
(not spelling though, that achievement remains well out of reach)
<whitequark>
nice!
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<Peanut>
Is it possible to extend the platform.resources by adding a new Resource? I get "unsupported operand type for +=: collections.orderedDict and Resource
<miek>
Peanut: yep, you can call platform.add_resources(...)
<Peanut>
Thanks - and wrap the resource in a list, it seems. That may have worked, let's see.
<Peanut>
Nice, I can even platform.request() it now.
<Peanut>
Not sure if I prefer 'm.d.sync += rgb.r.eq(0)' over 'r_led <= 0;' ...
<agg>
You're missing the sensitivity list part of the verilog :p
<whitequark>
and the perl scripts used to generate code that you no longer need, yeah
<agg>
(note you can add a whole list of assignments to a domain, like m.d.sync += a.eq(b), c.eq(d), e.eq(f)
<whitequark>
less facetiously, the way the Amaranth DSL is structured lets you metaprogram in a way much clearer than `generate` statements or textual composition/substitition
<whitequark>
you pay the cost in somewhat uglier syntax for the simpler cases and you gain the clarity in the more complex ones
<Peanut>
Ok - working my way up to the more complex ones any way.
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<lofty>
The decoder for my VAX core needs lots of information about the operands of an instruction
<lofty>
With amaranth that amounts to looping over a central python dictionary, keeping only the relevant entries, and then using `with m.If(opcode == ...)`
<lofty>
Plus I've found in a lot of cases if you're willing to give up signal naming, you can just use Python for Amaranth expressions
<lofty>
tiltmesenpai[m]: and amaranth will infer the signal name from the left hand side of a Python assignment, as long as there's only one
<lofty>
e.g `x = Signal()` gets name inferred to be x
<tiltmesenpai[m]>
oh, I'm talking about if you're doing things that cause amaranth to fail to derive a signal name
<tiltmesenpai[m]>
I assume that's what you mean by using Python for Amaranth expressions
<lofty>
If you look at the operand decoder you'll see what I mean
<lofty>
I don't create Signals and then `m.d.comb +=` them
<tiltmesenpai[m]>
hmm my brain's struggling to think here lol... I think I get what you're saying but I'm not sure
<lofty>
If you have two Signals a and b
<lofty>
Then you could do `x = Signal(); m.d.comb += x.eq(a + b)`
<lofty>
Or you could do `x = a + b`
<tiltmesenpai[m]>
oh yeah ok that's what you're saying. Yeah I also prefer doing things that way, until I need to debug something
<tiltmesenpai[m]>
then I end up reverting to explicit signals until I figure out what's wrong
<d1b2>
<hub.martin> Hi, I'm having some issues of porting LiteX to Lattice ECP5 VIP processor board. I have added SPI FLASH support but when I enable DDR3, the bitstream works (LED chaser works
<_whitenotifier-8>
[amaranth] cestrauss opened issue #671: cxxsim: ValueError: 4 is not a valid cxxrtl_type - https://git.io/JyZEw
<d1b2>
<hub.martin> Hi, I'm having some issues of porting LiteX to Lattice ECP5 VIP processor board. I have added SPI FLASH support but when I enable DDR3, the bitstream works (LED chaser works) but the new BIOS does not output anything on UART. When I load older BIOS without the DDR3 support (but with the new DDR3 bitstream) the BIOS starts correctly. Wehn I compare the objdump of ELF bios files, the linker addresees points correctly to SPI flash..