azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<kittennbfive>
Hello! I am using Yosys with the "synth_ecp5" command. Is there a way to specify an additional parameter/argument (make_outreg) to the map_bram-pass? Or asked otherwise, how can i tell Yosys to use REGMODE(OUTREG) on automatically instantiated block RAM?
<gatecat>
Yosys doesn't support 'extra' BRAM output registers afaik
<mwk>
yeah, not supported yet, and there are no plans for now
<kittennbfive>
Ok, so if i want REGMODE(OUTREG) i have to manually instantiate the EBR, is this correct?
<mwk>
right
<kittennbfive>
ok, thanks.
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