azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<tnt> Mmm. I'm getting AssertionError: Assertion failure: port.net == nullptr (/home/tnt/projects/fpga/toolchain/nextpnr/common/design_utils.cc:94) when calling ctx.connectPort(nn.name, d.cell.name, 'D')
<tnt> but I a ctx.disconnectPort(d.cell.name, 'D') the line right before so ...
<tnt> What's weird is that this looks exactly like what 3573fcca80669c390b002c17ede911fb73c8bbbf fixed > 1 year ago.
<tnt> Err yeah, not sure how/why but disconnect doesn't work anymore.
<tnt> disconnect_port() _does_ get called but at some point, some where ... it gets reconnected.
<tnt> wtf ...
<tnt> print(d.cell.name)
<tnt> ctx.disconnectPort(d.cell.name, 'D')
<tnt> print(d.cell.name)
<tnt> the 2 prints don't print the same thing ...
<gatecat> can you provide a bit more context ?
<tnt> which basically looks for LUTs output going to multiple FFs and replicate them so the LUT can be packed with the FF.
<tnt> and line 66, I added the print(d.cell.name) before and after the disconnect and ... it magically changed.
<gatecat> I think the problem is that disconnecting the port invalidates 'd', which is a reference to an entry in the net's user array
<gatecat> this is a horrible trap, I think I can fix it by passing PortRef's into Python by value
<gatecat> tnt: does https://github.com/YosysHQ/nextpnr/pull/805 fix it ?
<tnt> gatecat: yup.
<tnt> Tx :D
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