azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs:
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<Degi> Just in case anybody wondered: The ECP5 fabric of the -5G on my ECP5 EVN board can do at least 1800 MHz fabric speed (two :2 dividers chained in two clock domains)
<Degi> (I generated the clock with the SERDES of another ECP5)
<Degi> Got to 2100 MHz with some optimization of the clocked fabric
<gatecat> nice!
<Degi> (I mean apparently the IO buffers can only do 400 MHz according to the datasheet lol)
<Degi> I wonder if it can output that much too
<Degi> Well, 2150 MHz with reset_less=True on the nMigen clock domains
<Degi> And whether it works or not seems to depend on the synthesis seed lol
<agg> 2100MHz :o
<agg> what timing did nextpnr estimate?
<Degi> Like 1100 to 1300 MHz
<Degi> But the 2100 to 2150 MHz really seems to depend on synthesis luck
<Degi> Now the synthesis was particularly lucky and it got to 2187 MHz
<Degi> I wonder if you can transmit WiFi with the LVDS IO by taking the second or third harmonic
<Degi> (Well, these tests are for receive)
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<agg> or I guess which is bluetooth transmit from ecp5 serdes
<agg> except in your case the fabric itself is almost fast enough...
<Degi> Pretty sure that 2250 MHz is the max frequency of the IO (or of the ECLK dividers)
<Degi> heh nice, yes kinda
<Degi> Sadly the SERDES RX seems to be too broken to use as RF decoder... But maybe you can do subharmonic receive with LVDS RX?
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<agg> yea, i think that problem is why is xilinx
<agg> "I wish so much that this would work on a Lattice platform but there's no easy way to get Lattice SERDES blocks to lock to a reference rather than the incoming data. By setting a register, you can theoretically tell it to lock to the clock reference, but realistically it just instead runs RX clocked by an unstable ring oscillator. Now that I've got this all working on Xilinx, perhaps I can get back to
<agg> trying to get this to work on Lattice parts."
<agg> frustrating
<Degi> Different IOs seem to have different fmax
<Degi> Yes, I wonder if thats a silicon bug
<Degi> Or maybe the RX has no PLL from the REFCLK which can work without CDR?
<Degi> Putting TX PLL to RX would be ideal...
<Degi> O.o what, on B2/C2 instead of F2/E2 I got to 2550 MHz (not the fabric, just eclkdiv)
<Degi> The bluetooth thingie might have some hope after all
<Degi> Hm okay, the fabric seems to only be good to 2.25 GHz... I gotta test the TX another time with a loopback, I mean thats almost PCIe Gen 2 speeds. Though only some IOs seem to support it, I guess it depends on where in the chip they are and PVT and how lucky your compilation is (I added -r to the nextpnr_opts)
<Degi> Hm okay, the serdes PLL tops out at 5600 MHz. But the IO can sorta do that, though it gets pretty noisy (as in high jitter)
<Degi> Ah, that jitter might be due to the SERDES PLL being out of range.
<Degi> Ooh, I should try a ring oscillator with for example pins C1, D1 outputting ~(B2, C2) and then connecting it.
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<tpw_rules> agg: that bt stuff is super neat
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<Degi> Hmh, somehow I can't get a differential IO to output something
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<Degi> I see, I was executing the wrong python file.
<agg> was interesting too, looks like he got ~2GHz logic speed there too
<Degi> Ooh niice
<Degi> Good to know that you can instantiate slices like that
<agg> and also, delay line on an ecp5 with ~50ps resolution
<agg> and manual slice placement
<Degi> Has somebody yet implemented a PLL like that on the ECP5?
<agg> a logic pll? interesting
<Degi> I heard some company did that
<Degi> Considering how much noise lattice PLLs have, they might have tpoo
<Degi> *too
<Degi> Basically you adjust the length of the delay and make a ring oscillator
<agg> and change the delay taps to adjust the "vco" freq?
<Degi> Yes
<agg> seems pretty cursed
<Degi> I made a ring oscillator with IOs, somehow it only gets to 130 MHz and has suspiciously low jitter, like 25 ns per 100 µs
<Degi> Does anybody know what a step of the delayfis?
<Degi> *how many ps a step of the DELAYF has
<gatecat> I think I saw it was nominally 25ps according to one of the lattice docs
<Degi> I seemingly can see the dielectric absorption of water, or its high e_r by touching the twisted pair which is currently carrying 1.2 GHz (the signal stops) lol
<gatecat> haha
<Degi> Somehow I can't get a LVCMOS33D faster than 1450 MHz
<Degi> Seems the LVDS buffers are a bit faster, at 2100 MHz
<gatecat> output?
<Degi> Yes
<Degi> The input seems to be able to go a bit above 2.8 GHz
<gatecat> that would figure, LVCMOS33D re-uses the single ended output drivers in pseudo-diff mode, LVDS is a separate true differential output driver
<Degi> Can confirm 25 ps delay step
<Degi> Turns out you can wire a DELAYF in a loop with some physical wires
<sorear> can use as a TRNG :)
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