15:22 <Degi> Just in case anybody wondered: The ECP5 fabric of the -5G on my ECP5 EVN board can do at least 1800 MHz fabric speed (two :2 dividers chained in two clock domains)

15:22 <Degi> (I generated the clock with the SERDES of another ECP5)

15:31 <Degi> Got to 2100 MHz with some optimization of the clocked fabric

15:31 <gatecat> nice!

15:32 <Degi> (I mean apparently the IO buffers can only do 400 MHz according to the datasheet lol)

15:33 <Degi> I wonder if it can output that much too

15:35 <Degi> Well, 2150 MHz with reset_less=True on the nMigen clock domains

15:35 <Degi> And whether it works or not seems to depend on the synthesis seed lol

15:38 <agg> 2100MHz :o

15:38 <agg> what timing did nextpnr estimate?

15:39 <Degi> Like 1100 to 1300 MHz

15:40 <Degi> But the 2100 to 2150 MHz really seems to depend on synthesis luck

15:44 <Degi> Now the synthesis was particularly lucky and it got to 2187 MHz

15:45 <Degi> I wonder if you can transmit WiFi with the LVDS IO by taking the second or third harmonic

15:45 <Degi> (Well, these tests are for receive)

15:48 <agg> sorta like https://twitter.com/newhouseb/status/1369468611430088712 ?

15:50 <agg> or I guess https://twitter.com/newhouseb/status/1352796299700162560 which is bluetooth transmit from ecp5 serdes

15:50 <agg> except in your case the fabric itself is almost fast enough...

15:52 <Degi> Pretty sure that 2250 MHz is the max frequency of the IO (or of the ECLK dividers)

15:52 <Degi> heh nice, yes kinda

15:53 <Degi> Sadly the SERDES RX seems to be too broken to use as RF decoder... But maybe you can do subharmonic receive with LVDS RX?

15:54 <agg> yea, i think that problem is why https://github.com/newhouseb/onebitbt is xilinx

15:54 <agg> "I wish so much that this would work on a Lattice platform but there's no easy way to get Lattice SERDES blocks to lock to a reference rather than the incoming data. By setting a register, you can theoretically tell it to lock to the clock reference, but realistically it just instead runs RX clocked by an unstable ring oscillator. Now that I've got this all working on Xilinx, perhaps I can get back to

15:55 <agg> trying to get this to work on Lattice parts."

15:55 <agg> frustrating

15:55 <Degi> Different IOs seem to have different fmax

15:56 <Degi> Yes, I wonder if thats a silicon bug

15:56 <Degi> Or maybe the RX has no PLL from the REFCLK which can work without CDR?

15:56 <Degi> Putting TX PLL to RX would be ideal...

15:58 <Degi> O.o what, on B2/C2 instead of F2/E2 I got to 2550 MHz (not the fabric, just eclkdiv)

15:58 <Degi> The bluetooth thingie might have some hope after all

16:02 <Degi> Hm okay, the fabric seems to only be good to 2.25 GHz... I gotta test the TX another time with a loopback, I mean thats almost PCIe Gen 2 speeds. Though only some IOs seem to support it, I guess it depends on where in the chip they are and PVT and how lucky your compilation is (I added -r to the nextpnr_opts)

16:12 <Degi> Hm okay, the serdes PLL tops out at 5600 MHz. But the IO can sorta do that, though it gets pretty noisy (as in high jitter)

16:12 <Degi> Ah, that jitter might be due to the SERDES PLL being out of range.

16:13 <Degi> Ooh, I should try a ring oscillator with for example pins C1, D1 outputting ~(B2, C2) and then connecting it.

18:10 <tpw_rules> agg: that bt stuff is super neat

19:05 <Degi> Hmh, somehow I can't get a differential IO to output something

19:08 <Degi> I see, I was executing the wrong python file.

19:12 <agg> https://gist.github.com/newhouseb/4cf7dfb7bf1e0b6adf80005c6c6d9f39 was interesting too, looks like he got ~2GHz logic speed there too

19:13 <Degi> Ooh niice

19:14 <Degi> Good to know that you can instantiate slices like that

19:14 <agg> and also https://gist.github.com/newhouseb/784cc0c24f8681c3224c15758be5d1b8, delay line on an ecp5 with ~50ps resolution

19:14 <agg> and manual slice placement

19:14 <Degi> Has somebody yet implemented a PLL like that on the ECP5?

19:14 <agg> a logic pll? interesting

19:14 <Degi> I heard some company did that

19:14 <Degi> Considering how much noise lattice PLLs have, they might have tpoo

19:14 <Degi> *too

19:14 <Degi> Basically you adjust the length of the delay and make a ring oscillator

19:15 <agg> and change the delay taps to adjust the "vco" freq?

19:15 <Degi> Yes

19:15 <agg> seems pretty cursed

19:16 <Degi> I made a ring oscillator with IOs, somehow it only gets to 130 MHz and has suspiciously low jitter, like 25 ns per 100 µs

19:20 <Degi> Does anybody know what a step of the delayfis?

19:20 <Degi> *how many ps a step of the DELAYF has

19:21 <gatecat> I think I saw it was nominally 25ps according to one of the lattice docs

19:35 <Degi> I seemingly can see the dielectric absorption of water, or its high e_r by touching the twisted pair which is currently carrying 1.2 GHz (the signal stops) lol

19:35 <gatecat> haha

19:43 <Degi> Somehow I can't get a LVCMOS33D faster than 1450 MHz

19:49 <Degi> Seems the LVDS buffers are a bit faster, at 2100 MHz

19:50 <gatecat> output?

19:50 <Degi> Yes

19:50 <Degi> The input seems to be able to go a bit above 2.8 GHz

19:50 <gatecat> that would figure, LVCMOS33D re-uses the single ended output drivers in pseudo-diff mode, LVDS is a separate true differential output driver

20:30 <Degi> Can confirm 25 ps delay step

20:42 <Degi> Turns out you can wire a DELAYF in a loop with some physical wires

20:47 <sorear> can use as a TRNG :)