azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
specing_ has joined ##openfpga
specing has quit [Killed (NickServ (GHOST command used by specing_))]
specing_ is now known as specing
Degi_ has joined ##openfpga
Degi has quit [Ping timeout: 272 seconds]
Degi_ is now known as Degi
cr19011 has joined ##openfpga
cr1901 has quit [Ping timeout: 250 seconds]
cr19011 is now known as cr1901
emeb_mac has quit [Ping timeout: 258 seconds]
emeb_mac has joined ##openfpga
kittennbfive has joined ##openfpga
<kittennbfive>
Hello again. Simple question about memory in Verilog (Yosys, ECP5): Is it legal to use an "initial"-statement to initialize one entry of the memory/array to some value? Like "reg missed_event [15:0]; initial missed_event[0]<=0;" ?
<kittennbfive>
And if yes, is it legal too to initialize several different positions inside the initial begin ... end?
<kittennbfive>
uh nevermind, one day after i build my Yosys version there was a fix for the bug i found.
kittennbfive has quit [Quit: Leaving]
emeb_mac has quit [Quit: Leaving.]
somlo_ has joined ##openfpga
peeps[zen] has joined ##openfpga
npcomp has quit [Ping timeout: 245 seconds]
buhman has quit [Ping timeout: 256 seconds]
iximeow_ has quit [Ping timeout: 252 seconds]
iximeow has joined ##openfpga
peepsalot has quit [Ping timeout: 256 seconds]
somlo has quit [Remote host closed the connection]