whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Adrien[m]> I'm not familiar with ecp5 DSPs, but this behaviour could be a different number of pipeline regs within the DSP for data inputs and for the SIGNED inputs
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<gatecat> it's a shame the lattice sim models for the DSPs are such a mess
<gatecat> maybe I should still try and see if I can figure out anything there
<gatecat> can't reproduce this with a quick testbench using their sim model, so I guess it would be hardware testing time to investigate this further...
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<juri_> gatecat: do keep us posted, I'm just assembling a lattice test machine myself.
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