<tpb>
Title: Setting up a flow for ABC9 - YosysHQ Yosys 0.44-dev documentation (at yosyshq.readthedocs.io)
<lofty>
(which is all done as part of the Gowin simulation library, so you can just do `read_verilog -lib -specify +/gowin/cells_sim.v`)
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<Adrien[m]>
Hi, about abc9 I'd like to raise a questionWith an intern we've noticed that activating abc9 with `synth_xilinx` can produce a much larger design, by something like 2.5x when summing LUT counts in final resource usage report (will be able to confirm once holidays are over).
<Adrien[m]>
I know abc9 flow is marked experimental, but to that extent really ?
<Adrien[m]>
RAM usage and processing time are also much higher.
<lofty>
Adrien[m]: I think I might know why
<lofty>
more or less, delay and area are inversely correlated; a lower-delay solution consumes more area because there is less timing slack available
<lofty>
my suspicion is that ABC9 has found a *much* lower-delay solution than ABC, and as a result, area went up
<lofty>
if you add `scratchpad -set abc9.D N` (where N is a delay target in picoseconds; I would say roughly half your intended clock period), then you should be able to recover a lot of area
<gatecat>
this might also be a consequence of synth_xilinx not flattening the design
<gatecat>
this means you generally have more, smaller modules, so the critical path that ABC sees is shorter
<gatecat>
and therefore it's more aggressively optimising for delay than it needs to, particularly as it can't see the "real" critical path as all it sees are the individual submodules
<gatecat>
you could compare the two with -flatten as well and see if there's a difference - usually I'd expect a decent improvement with abc9 on xilinx, because it tends to be more sensible about using wide LUTs (MUXF7/8)
<Adrien[m]>
lofty gatecat Thank you for the insight. We will have a look.
<lofty>
Adrien[m]: who's "we" in this instance?
<Adrien[m]>
The intern and me. Probably mostly me given that the intern will have his next year to begin
<Adrien[m]>
In the end we decided to always keep the hierarchy in test designs, because designs were not worse, and RAM usage and synth time were much lower. This is critical when doing synthe
<Adrien[m]>
... synthesis within embedded system and under 512 MB of RAM total