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<famubu[m]>
<lofty> "If you run "help synth_gowin..." <- Oh... I see it now..
<famubu[m]>
<lofty> "But if you're just trying to..." <- 👍️ That was my primary aim.
<famubu[m]>
<lofty> "If you're doing this to learn..." <- Also interested in this. Been reading the yosys manual from here and there.
<famubu[m]>
<lofty> "LUT5/6/7/8: it's true that Gowin..." <- Ah.. right.
<famubu[m]>
<lofty> "(which is all done as part of..." <- That what should be used? Not`read_verilog file.v; synth_gowin -top top -json top.json`?
<famubu[m]>
* That's what, * used? Not `read_verilog file.v;
<famubu[m]>
And I didn't totally get what specify does in verilog. I mean, it says it's for mentioning some delay in a module. But what delay? And where does it come in handy?
<famubu[m]>
Are specify blocks used only during timing?
<famubu[m]>
* Are specify blocks used only during timing analysis? They are otherwise inert?
<lofty>
famubu[m]: yes, they're mainly used in timing analysis, although they're also used in some cases to describe possible paths through cells, such as flops.
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