whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<famubu[m]> Oh..
<famubu[m]> Can static timing analysis be done without cell library?
<famubu[m]> I was looking at OpenTimer. And it seems to require cell library?
<famubu[m]> Timing analysis is relevant for FPGAs as well, right?
<famubu[m]> Wait.. Does nextpnr do timing analysis as well?
<famubu[m]> I guess this is something related: share/yosys/gowin/cells_map.v
<whitequark[cis]> nextpnr does timing analysis, yes
<whitequark[cis]> timing analysis for FPGAs is done in a completely separate way from ASICs
<famubu[m]> I guess opentimer is for ASIC then..
<famubu[m]> Is there some place I can read a little about differences in doing timing analysis for ASIC vs that of FPGA?
<bjorkintosh> opentimer. perhaps if one is created for FPGA it should be called instead of opentimer, openheimer!
<bjorkintosh> sorry famubu[m]. I know next to nothing myself.
<famubu[m]> 😅
<famubu[m]> I found that tool upon a random google search: https://github.com/OpenTimer/OpenTimer
<famubu[m]> Is yosys abc command for logic optimization not applicable for FPGA designs?
<bjorkintosh> it has to be.
<whitequark[cis]> abc is used for FPGAs
<whitequark[cis]> just in different mode
<famubu[m]> Oh.. sorry, I had been thinking the -liberty argument was mandatory for abc command. It's not.
<lofty> Ideally abc9 is used for FPGAs
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