<famubu>
Hi. I'm new to hardware synthesis and was wondering about liberty files. Does the liberty file correspond to any particular board? Or is it generic?
<lofty>
famubu: they correspond to a specific ASIC process
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<famubu[m]>
Oh is it applicable only for ASIC? I was trying to do for FPGA.
<famubu[m]>
Is there some place where I can read up about this?
<lofty>
famubu[m]: which FPGA? that's an important first step
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<famubu[m]>
gowin. Sipeed Tang nano
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<famubu[m]>
Does that mean it does depend on the FPGA? Or does the kind of process also depend on the FPGA?
<famubu[m]>
(And what does ASIC proces mean? Isn't it same for all ASICs? Broadly speaking.)
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<lofty>
[17:04:35] famubu[m]: gowin. Sipeed Tang nano <--- we already have `synth_gowin` for that
<lofty>
As for the others, I'm going to answer them in reverse
<somlo>
lofty: while you're at it, I'm slightly confused about terminology: are "liberty files" a component of an ASIC process (a.k.a. "PDK") (i.e., in addition to a bunch of other stuff making up the PDK, or else what's the conceptual relationship between all these terms? :)
<lofty>
[17:05:55] famubu[m]: (And what does ASIC proces mean? <--- feature size, types of gates, sizing of gates; these all affect input capacitance, propagation delay, and output slew. these are all things specific to Liberty standard cell libraries and the processes they use.
<lofty>
[17:05:55] famubu[m]: Isn't it same for all ASICs? Broadly speaking. <--- no; smaller processes will have smaller gates, with less input capacitance, faster propagation delay, and such. cutting-edge processes have FinFETs and GAAFETs. those are not something earlier processes can fabricate.
<lofty>
[17:05:40] famubu[m]: Does that mean it does depend on the FPGA? Or does the kind of process also depend on the FPGA? <--- an FPGA will be designed for and use a specific process, so yes. migration between processes is rare, but has been done (Lattice ECP5)
<lofty>
somlo: Liberty files contain all the properties of the cells of a standard cell library, but not the physical design of them. So yes, they are part of the PDK. Yosys (and more specifically ABC) use the data inside them to decide between a bunch of different ways of implementing the same circuit.
<somlo>
lofty: thanks, so essentially an "extracted" view of cells in the library, so that logic optimization (e.g. delay) decisions can be made during synthesis?
<lofty>
somlo: yes; extraction is an excellent term for it.
<somlo>
they made us use cadence for a class I took, that's what it's called there :)
<lofty>
Liberty is a Synopsys format, but they released it openly (hence the name)
<lofty>
somlo: any other questions? :p
<somlo>
nope, I think I'm starting to associate the right words with the proper concepts, so thanks :D
<somlo>
lofty: actually, I have another one: besides nextpnr (lattice) and nextpnr-xilinx (which I'm about to start poking at to see if I can get some traction out of), are there any other F/OSS P&R programs that are part of yosyshq (e.g., for any of the ASIC PDKs)? Or is all (most?) of it currently limited to synthesis and logic optimization?
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<lofty>
somlo: nextpnr-xilinx is dead; I know people have tried to resurrect it, but it's diverged significantly from upstream and it seems like it's considered a developmental dead end.
<lofty>
somlo: as for the second question: no, but we have been working with the OpenROAD and efabless' OpenLane teams for ASIC things.
<lofty>
to be honest: even nextpnr is lacking person-power.
<somlo>
by "developmental dead end" (re. nextpnr-xilinx), you mean xilinx P&R (along with prjxray) is now "abandonware", or are there plans/efforts to support xilinx P&R as part of some other tool or project?
<lofty>
I can't comment on the status of prjxray, but the git log doesn't fill me with much hope
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<somlo>
re nextpnr PR 1235: I notice it's been merged; appears to require prjxray-db to build (reasonable of course) -- any idea what the "canonical" board being used to test might be ? Some version of Arty A7 perhaps?