whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<somlo> silly cmake question (re nextpnr/himbaechel/xilinx): I ran `cmake . -DARCH="himbaechel" -DHIMBAECHEL_XILINX_DEVICES="all" -DHIMBAECHEL_PRJXRAY_DB="../prjxray-db"` and toward the end it's complaining about being unable to find '../prjxray-db/artix7/all/tilegrid.json' :)
<somlo> Do I really have to enumerate all Artix7 (and whatever else) devices, or is there some other way to specify that I want all of them on the cmake command line ?
<somlo> hmm, going by the gowin example, they do have a special-case where `all` points to a full pre-enumerated list in the CmakeLists file, but they only have like 8 devices or so
<somlo> in comparison, the xilinx artix7 list is *HUGE* :)
<somlo> guess this is another question for gatecat...
<somlo> this is the part where knowing which board is "canonical" for the xilinx/himbaechel commit (5bfe0dd1) would allow me to specify the right artix7 model for an initial attempt to get *something* working as a starting point...
<gatecat> somlo: I haven't touched himbaechel-xilinx for a while, so this is a bit rusty
<gatecat> but I'm pretty sure I was testing on an arty 35t
<gatecat> but yeah, no way of building for all devices atm
<gatecat> I think that's xc7a35t on the command line
<somlo> there's 91 of them in prjxray-db right now, so that'd be a hefty HIMBAECHEL_XILINX_ALL entry in the cmake file :D (no point in adding that at this early stage, so I'll try xc7a35t only for now)
<gatecat> or indeed, xc7a50t actually :P
<gatecat> the 35t is a fake device
<somlo> I remember having a 35t sitting around in a box somewhere, I'll go try to dig it up
<gatecat> and apparently I already special-cased the lookup there
<somlo> not sure they're still for sale (in case I don't find it) -- all digilent lists right now is a 100t board
<somlo> I remember something about the 35t being a software-lobotomized 50t from a conversation way back...
<somlo> gatecat: there's 20 variants of the xc7a35t* (and 21 of the xc7a50t*) in prjxray-db, and it looks like I need to spell out the exact sub-variant on the cmake setup line...
<somlo> guess I'll need to find the board and look at the actual chip markings if I'm to pick the right one...
<somlo> made it as far as "xc7a35tcsg324-" -- there's "-1", "-2", "-2L", and "-3", not sure which one based on the markings -- https://imgur.com/a/454o7UU
<tpb> Title: Imgur: The magic of the Internet (at imgur.com)
<somlo> apparently it's the "L1|" that's relevant, and the datasheet says I should probably go with the "-1" speed grade, so that's my best guess right now...
<somlo> ok, answering my own question -- no need to specify speed grades, but there needs to be a tilegrid.json file under the model name. so xc7a35t doesn't have one, had to go for xc7a50t (knowing it's the same thing underneath)
<somlo> in conclusion, `cmake . -DARCH="himbaechel" -DHIMBAECHEL_XILINX_DEVICES="xc7a50t" -DHIMBAECHEL_PRJXRAY_DB="/full/path/to/prjxray-db"` works, followed by `cmake --build . --verbose` for the actual compile run
<somlo> now, let's see what happens when I try to actually use it, fingers crossed :)
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<somlo> nextpnr-himbaechel (built for xilinx) seems to expect a `-json` file to ingest, but (at least by default), yosys' `synth_xilinx` will only output edif or blif
<somlo> what to do? Can I just follow up `synth_xilinx` with an explicit `write_json` command, or is there more to it than that ?
<lofty> somlo: yeah, it's that simple
<somlo> nice, thanks!
<somlo> ok, I have a json file ready for nextpnr-himbaechel. With ecp5, there was a `-lpf <board_file>` option to specify pin constraints; however, for the arty board, all I have is an xdc file which contains the same pin data, and no obvious clue as to how I'd pass that into nextpnr
<somlo> s/same pin data/same *kind* of pin data, for the arty rather than the ecpix/
<somlo> or do I have to (for now, with the early dev. state of xilinx support) pass raw fpga pin names directly to the toplevel verilog module? (in which case, does anyone have an example of the syntax I can use as inspiration)?
<somlo> e.g., on the arty, user_led0 is mappped to pin H5, user_led1 to J5, etc., and clk100 is E3; Would `module top( input E3, output H5, output J5, ...` be all I need, or am I out-thinking myself again? :)
<somlo> nvm, I found the blinky.sh example added with the himbaechel-xilinx patch, complete with additional optimizations on the yosys command line, *and* instructions on how to specify the xdc file :)
<somlo> sorry for the noise :)
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