whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Adrien[m]> Hi Guys, I've hit an issue with yosys techmap for Xilinx :
<Adrien[m]> `/usr/bin/../share/yosys/xilinx/cells_map.v:151: ERROR: Signal `\A' with invalid width range -1!`
<Adrien[m]> s/`\/'\\/, s/!`/!\`/
<Adrien[m]> I'm not sure this originates from my design or if it's a Yosys issue.
<Adrien[m]> Is there a specific message to look for in Yosys log to get a candidate hint ?
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<Adrien[m]> Next issue : Yosys plainly rejects designs that use task `$fatal`
<Adrien[m]> (actually these occurrences are generated from ghdl from conversions of asserts)
<Adrien[m]> Shouldn't these be just ignored instead ?
<Adrien[m]> Yosys error message is : ERROR: Can't resolve task name '$fatal'
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