ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
so-offish has quit [Ping timeout: 240 seconds]
|{ame has joined #yosys
mewt has joined #yosys
TD-Linux has quit [Ping timeout: 255 seconds]
_whitelogger has quit [Ping timeout: 240 seconds]
mewt has quit [Ping timeout: 240 seconds]
_whitelogger_ has joined #yosys
_whitelogger_ has quit [Ping timeout: 240 seconds]
_whitelogger has joined #yosys
acathla has joined #yosys
nonchip has joined #yosys
bjorkint0sh has joined #yosys
FL4SHK has joined #yosys
sorear_ has joined #yosys
bjonnh has quit [Ping timeout: 240 seconds]
bjonnh has joined #yosys
Raito_Bezarius has quit [Client Quit]
Raito_Bezarius has joined #yosys
Raito_Bezarius has quit [Read error: Connection reset by peer]
ymherklotz has joined #yosys
Raito_Bezarius has joined #yosys
Raito_Bezarius has quit [Client Quit]
Raito_Bezarius has joined #yosys
lofty has joined #yosys
cr1901_ has joined #yosys
Raito_Bezarius has quit [Client Quit]
Raito_Bezarius has joined #yosys
jleightcap has joined #yosys
srk has joined #yosys
Raito_Bezarius has quit [Client Quit]
Raito_Bezarius has joined #yosys
Lord_Nightmare has joined #yosys
corecode has joined #yosys
Zaba has joined #yosys
TD-Linux has joined #yosys
anticw has joined #yosys
cr1901_ is now known as cr1901
muuo has joined #yosys
heath2 has joined #yosys
Raito_Bezarius has quit [Quit: free()]
Raito_Bezarius has joined #yosys
tnt has joined #yosys
srk- has joined #yosys
Raito_Bezarius has quit [Ping timeout: 255 seconds]
anticw has quit [Ping timeout: 255 seconds]
Lord_Nightmare2 has joined #yosys
tnt has quit [Ping timeout: 255 seconds]
srk has quit [Ping timeout: 255 seconds]
Lord_Nightmare has quit [Ping timeout: 255 seconds]
anticw has joined #yosys
tnt has joined #yosys
Raito_Bezarius has joined #yosys
srk- is now known as srk
Lord_Nightmare2 is now known as Lord_Nightmare
cr1901 has quit [Read error: Connection reset by peer]
cr1901 has joined #yosys
Raito_Bezarius has quit [Ping timeout: 255 seconds]
tnt has quit [Ping timeout: 255 seconds]
tnt has joined #yosys
Raito_Bezarius has joined #yosys
citypw has joined #yosys
tux3 has quit [Ping timeout: 240 seconds]
tux3 has joined #yosys
ec_ has quit [Ping timeout: 240 seconds]
ec_ has joined #yosys
|{ame has quit [Quit: Client closed]
ZipCPU has quit [Server closed connection]
ZipCPU has joined #yosys
schaeg has joined #yosys
fayalalebrun has joined #yosys
<fayalalebrun> Hello, I'm learning formal verification using GHDL, PSL, and Simbiyosys. I was wondering why the following code fails the induction step:
<fayalalebrun> f_reset : assume {reset_in};
<fayalalebrun> f_no_reset : assume next (always not reset_in);
<fayalalebrun> f_no_reset_a : assert next (always not reset_in);
<fayalalebrun> My intent is to assume reset is only asserted at the start of the trace. Why would the assertion here fail? Do assumptions not apply during induction?
FabM has joined #yosys
FabM has quit [Changing host]
FabM has joined #yosys
TianruiWei[m] has quit [Read error: Connection reset by peer]
jryans has quit [Write error: Connection reset by peer]
charlottia has quit [Read error: Connection reset by peer]
jevinskie[m] has quit [Write error: Connection reset by peer]
whitequark has quit [Read error: Connection reset by peer]
bjonnh[m] has quit [Read error: Connection reset by peer]
programmerjake has quit [Read error: Connection reset by peer]
pepijndevos[m] has quit [Write error: Connection reset by peer]
xiretza[m] has quit [Read error: Connection reset by peer]
xiretza[m] has joined #yosys
pepijndevos[m] has joined #yosys
programmerjake has joined #yosys
whitequark has joined #yosys
jryans has joined #yosys
jevinskie[m] has joined #yosys
bjonnh[m] has joined #yosys
charlottia has joined #yosys
TianruiWei[m] has joined #yosys
kristianpaul has quit [Quit: WeeChat 2.3]
kristianpaul has joined #yosys
FabM has quit [Quit: Leaving]
FabM has joined #yosys
FabM has joined #yosys
FabM has quit [Changing host]
<schaeg> Is some aware of any open source code base in Verilog-A, Verilog-AMS or VHDL-AMS (where the A isn't just for decoration)? Is someone aware whether one can write an VHDL/Verilog-AMS code in a foundary portable way?
schaeg has quit [Ping timeout: 248 seconds]
schaeg has joined #yosys
fayalalebrun has quit [Quit: Client closed]
vancz has quit []
vancz has joined #yosys
vancz has quit [Client Quit]
FabM has quit [Quit: Leaving]
vancz has joined #yosys
so-offish has joined #yosys
so-offish has quit [Remote host closed the connection]
citypw has quit [Ping timeout: 240 seconds]
bjorkint0sh has quit [Remote host closed the connection]
bjorkint0sh has joined #yosys
fayalalebrun has joined #yosys
Xark has quit [Server closed connection]
Xark has joined #yosys
fayalalebrun has quit [Quit: Client closed]
so-offish has joined #yosys
<so-offish> Oh I figured it out btw (the "Cell type is unsupported") :D
<so-offish> There was an error higher up (bad RTL) and once I fixed that we were handy dandy.
<so-offish> Sorry that was lame. "once I fixed that, it worked"
schaeg has quit [Ping timeout: 256 seconds]
nonchip has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
nonchip has joined #yosys