ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<keesj> Hi
<keesj> I am trying to do timing accurate simulation using iverilog. It it possible using yosys to read liberty file and generate verilog containing the delay information?
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<keesj> I am targetting sky130
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<gatecat> keesj: no, there's no ability inside yosys to deal with liberty timing (this is passed straight through to abc for synthesis)
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<keesj> I have seen some behavioural verilog file that do contain timing. any idea on where to get some / how to convert somehow?
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<keesj> So when yosys output the max frequency the device can run. What is this based on?
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<gatecat> do you mean yosys or nextpnr?
<gatecat> although yosys does have a sta command that can do this, it's not very widely used. it does indeed use the verilog timing information but that's very much fpga-oriented and was manually created, it can't load liberty timing
<gatecat> for an asic flow you might get some delay information from the liberty printed by abc, but yosys isn't involved there other than telling abc where the liberty file is...
<lofty> You'd want something like opensta for ASIC timing
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