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<
FL4SHK>
for some reason it appears that a Verilog `task` synthesizes to its arguments being driven with 'x
<
tpb>
Title: Paste.ee - View paste Vqveu (at paste.ee)
<
tpb>
Title: Paste.ee - View paste xIcpk (at paste.ee)
<
FL4SHK>
well, first I ran the first paste.ee link through `sv2v` by zachjs
<
FL4SHK>
I suppose I can just use regular `function`s
<
FL4SHK>
and have them return a `struct` data type
<
FL4SHK>
yosys should be able to handle that since sv2v converts structs to vectors
<
tnt>
hat is the sv2v output ?
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<
tpb>
Title: Paste.ee - View paste 1mivU (at paste.ee)
<
FL4SHK>
hm, wait a minute
<
FL4SHK>
yeah, looks like maybe yosys doesn't deal with tasks that well anyway...
<
FL4SHK>
at least not with arguments
<
FL4SHK>
is there a good way to invoke a yosys script from a makefile?
<
FL4SHK>
for like, different multiple designs
<
FL4SHK>
and can I provide arguments to a script?
<
FL4SHK>
guess I could just have the makefile generate a script
<
tnt>
Mmm, yeah looks like a bug.
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