ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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* knielsen found some numbers: 11 layers in IBM 90nm. 6 layers in intel 90nm, 9 layers in intel 90nm, 11/12 layers in TSMC 28nm
<Sarayan> metal layers or total layers? (there's the active and the polysilicon layer at the bottom)
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<knielsen> I think metal layers
<Sarayan> that doesn't seem insane
<knielsen> The TSMC numbers are from https://www.techinsights.com/blog/review-tsmc-28-nm-process-technology ("layers of metal in the backend"), the other numbers are from the book "CMOS VLSI design"
<tpb> Title: A Review of TSMC 28 nm Process Technology | TechInsights (at www.techinsights.com)
<knielsen> Oh, typo, I meant "9 layers in Intel 45 nm"
<knielsen> I'd assume that more advanced processes increase the number of layers. Or maybe there's a point of diminishing returns?
<Sarayan> if you have more transistors you tend to need more routing, I guess
<Sarayan> and perhaps since distances are less you can have more routing?
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<singham> In all ICs, there is just the 1 semiconductor layer?
<singham> base wafer?
<knielsen> singham: That's the way they are produced. The transistors are created with the bottom layers, and then metal layers go on top with the routing
<singham> There's no Y axis, sandwich type connections?
<singham> knielsen: Yes, are you sure? Say there is Ryzen 3. They use a single layer 7nm process?
<knielsen> there's vertical routing (called "vias"). And I think there's some instances where two (or more) individual chips are stacked on top of each other after wafer has been produced
<singham> Aha. How probable is that?
<singham> The stacking of wafers? Will there be say an AND gate on bottom layer, OR on above layer and connect both?
<tnt> Well you have fancy process to stack multiple layers ( 3D NAND / X3D amd parts / ... ) but they're made in 2d and then stacked.
<knielsen> singham: It's inherent in the process by which the wafer is produced. You start with the pure silicon crystal in a thin slice ("wafer"). Then regions are doped to create the N and P regions that form the mosfet transistors. Then the gate goes on top (or a bit more complex for finfet etc), and metal layers are layed down on top of that. The transistors can only be created on the bottom layer on the silicon
<knielsen> crystal
<tpb> Title: Three-dimensional integrated circuit - Wikipedia (at en.wikipedia.org)
<singham> Interesting
<singham> Physical design is very complex compared to writing HDL
<singham> There are sizes of gates, adding buffers, splitting of signals, cross-talking between wires, clock skews and jitters, and a lot more!
<singham> knielsen: What do you do?
<singham> I mean, what is your work?
<singham> tnt and knielsen
<singham> Thanks folks
* singham will see you comrades later
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<so-offish> Hey everybody - if I open up nextpnr, an I just run a command that's like, rip everything up and start over again? Like go back to unpacked, unplaced, unrouted? Or maybe just unplaced/unrouted would be good enough...
<so-offish> I know "just look at the API" but I'm tired RN and if anybody just knows off the top of their head I'd appreciate it.