ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<singham> Standard cells, shouldn't they differ from foundry to foundry?
<singham> Say there's skywater pdk which creates library for skywater foundry for the specific conditions it has.
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<singham> If I go for fabricating an IC with AllWinner, for the same, say 130nm, it's cell dimensions, of length and breadth of transistors, etc. would be different right?
<singham> My question is AND gate at AllWinner foundry and AND gate at Intel Foundry should have different characteristics right, for same dimensions.
<singham> So my argument is shouldn't libraries should be different for all semiconductor foundries of the world?
<tnt> They are different ?
<tnt> Like each foundry provides their standard cell libs.
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<singham> Yes
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<tnt> (often several of them actually ... depending if you want low power / high speed / ... )
<singham> So say, I design an AND gate for skywater foundry, say it has 20nm width and 40nm high, with the right proportions for n doped, oxide, p doped all that
<singham> If I move that as it is to Intel foundry, won't my design falter?
<tnt> Depends on each process ... some are actually "kinda" compatible. Like for instance ECP5 was moved from one process to another. Athough done by different foundries those were compatible.
<tnt> (they did bunch of re-validation etc ... you can read about it in some pdf that I can't recall exactly how to find, but it's out there)
<singham> tnt: What do you do? Your work?
<tnt> I'm a FPGA designer. I don't do asic for work, this is just "basic" knowledge from dabbing into sky130 / gf180.
<singham> Wow! Cool, man!
<singham> I heard a nice joke by Clive on FPGAs
<singham> FPGA designers have so much complexity in routing and connections, that they throw in CLBs as a bonus!
<tnt> Ok, to be clear, what I meant is I do designs running on FPGA, I don't design the FPGA themselves. ( i.e. see the next sentence where I say "I don't do asic for work" ).
<singham> Aah ok :)
<singham> Nice.
<singham> Last 2 days I learnt quite a lot on physical design of FPGAs
<singham> Gowin semiconductor boards are quite powerful!
<singham> I saw lately, 20k LUTs.
<singham> I'm waiting for their SRAM ones to be supported by yosys nextpnr
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<so-offish> Whats up everyoen
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