ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<somlo> getting this failed test error when building on Fedora:
<somlo> Running syntax check on arch sim models
<somlo> [...]
<somlo> Test ../../techlibs/ecp5/cells_sim.v ->../../techlibs/ecp5/cells_sim.v:448: syntax error
<somlo> ../../techlibs/ecp5/cells_sim.v:448: error: invalid module item.
<somlo> make: *** [Makefile:865: test] Error 2
<somlo> ... but only happens on f36 and f37; on f38 and rawhide it works fine
<somlo> i did backport the latest abc package from rawhide to f36, still getting the error, so it's not abc :)
<somlo> any other ideas much appreciated (it's otherwise the same SRPM I'm using with mock for all the different fedora versions)
<somlo> hmmm -- iverilog got a few bumps between f36 and rawhide...
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<somlo> update: updating iverilog to 12.0 got the test to pass
<somlo> available in the soon-to-be-released F38 and onward